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Patent US5518959A successfully refreshed from Google Patents.
US5518959A
Expired / Lapsed
US
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Method for selectively depositing silicon oxide spacer layers
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-08-24
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Granted: 1996-05-21
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Expires: 2015-08-24
Abstract
Abstract A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within an integrated circuit. Formed upon a semiconductor substrate is a silicon oxide insulator substrate layer which is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer are formed multi-layer patterned metal stacks. The multi-layer patterned metal stacks have a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy. Formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stacks and upon the edges of the aluminum containing alloy exposed through the multi-layer patterned metal stacks is a silicon oxide insulator spacer layer. The silicon oxide insulator spacer layer is formed through an ozone assisted Chemical Vapor Deposition (CVD) process employing Tetra Ethyl Ortho Silicate as the silicon source material. The silicon oxide insulator spacer layer is formed for a deposition time not exceeding an incubation time for forming the silicon oxide insulator spacer layer upon the top barrier metal layer formed from titanium nitride.
Inventors
- 👤 Syun-Ming Jang
- 👤 Chen-Hua Yu
- 👤 Lung Chen
- 👤 Lin-June Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:22
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
175 words
A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within integrated circuits comprising: forming upon a semiconductor substrate a silicon oxide insulator substrate layer, the silicon oxide insulator substrate layer being formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process; forming upon the silicon oxide insulator substrate layer a multi-layer patterned metal stack, the multi-layer patterned metal stack comprising a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy; forming selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stack and upon the edges of the lower-lying conductor metal layer exposed through the multi-layer patterned metal stack a silicon oxide insulator spacer layer formed through an ozone assisted Chemical Vapor Deposition (CVD) process, the silicon oxide insulator spacer layer being formed for a deposition time not exceeding an incubation time for forming the silicon oxide insulator spacer layer upon the top barrier metal layer formed from titanium nitride.
Claim 2
Independent Claim
175 words
A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within integrated circuits comprising: forming upon a semiconductor substrate a silicon oxide insulator substrate layer, the silicon oxide insulator substrate layer being formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process; forming upon the silicon oxide insulator substrate layer a multi-layer patterned metal stack, the multi-layer patterned metal stack comprising a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy; forming selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stack and upon the edges of the lower-lying conductor metal layer exposed through the multi-layer patterned metal stack a silicon oxide insulator spacer layer formed through an ozone assisted Chemical Vapor Deposition (CVD) process, the silicon oxide insulator spacer layer being formed for a deposition time not exceeding an incubation time for forming the silicon oxide insulator spacer layer upon the top barrier metal layer formed from titanium nitride.
Claim 3
Dependent Claim
45 words
The method of claim 1 wherein the silicon oxide insulator substrate layer is formed through a Plasma Enhanced Chemical Vapor Deposition process which employs a silicon source material chosen from the group of silicon source materials consisting of silane and Tetra Ethyl Ortho Silicate (TEOS).
Claim 4
Dependent Claim
19 words
The method of claim 1 wherein the top barrier metal layer is about 1000 to about 1400 angstroms thick.
Claim 5
Dependent Claim
21 words
The method of claim 1 wherein the top barrier metal layer is formed through a Physical Vapor Deposition (PVD) sputtering method.
Claim 6
Dependent Claim
19 words
The method of claim 1 wherein the lower-lying conductor metal layer is about 4000 to about 6000 angstroms thick.
Claim 7
Dependent Claim
18 words
The method of claim 1 wherein the lower-lying conductor metal layer contains about 0.5 to about 1.0% copper.
Claim 8
Dependent Claim
24 words
The method of claim 1 wherein ozone assisted Chemical Vapor Deposition (CVD) process employs Tetra Ethyl Ortho Silicate (TEOS) as the silicon source material.
Claim 9
Dependent Claim
32 words
The method of claim 7 wherein the Tetra Ethyl Ortho Silicate is employed within the ozone assisted Chemical Vapor Deposition (CVD) process at an ozone:TEOS ratio of about 12:1 to about 20:1.
Claim 10
Dependent Claim
27 words
The method of claim 1 wherein the deposition time is equal to the incubation time, and the incubation time is from about 50 to about 55 seconds.
Claim 11
Dependent Claim
58 words
The method of claim 9 wherein the thickness of the silicon oxide insulator spacer layer is about 1300 to about 1500 angstroms over the surface of the silicon oxide insulator substrate layer and the thickness of the silicon oxide insulator spacer layer is about 1200 to about 1300 angstroms adjoining the edges of the lower-lying conductor metal layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-21 | 1999-11-20 | 2000-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-21 | 2003-11-20 | 2004-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-21 | 2007-11-20 | 2008-05-21 | $7700.00 | Window Closed / Lapsed |