Reducing errors in digital communication

Claim 3

The method of claim 7 wherein the two channels impose different delays on the communication of the information and the method further comprises compensating for the different delays prior to the selecting step.

Claim 4

The method of claim 1 wherein the incorporating step comprises organizing the information in blocks of bits and incorporating error checking information in each of the blocks of bits.

Claim 5

The method of claim 3 wherein the selecting step comprises making a selection for each of the blocks based on an error checking analysis of the error checking information in the block.

Claim 6

The method of claim 1 further comprising repeating, for the information selected in the selecting step, the steps of incorporating, sending, and selecting.

Claim 7

The method of claim 5 wherein the incorporating step comprises adding parity checking bits to the selected information.

Claim 8

The method of claim 1 wherein the step of selecting comprises determining a relative degree of error exhibited in the information sent on the two channels.

Claim 9

The method of claim 7 wherein the step of selecting comprises selecting one of the channels for which the information is not in error.

Claim 10

The method of claim 7 wherein the step of selecting comprises determining an average error rate over time for each of the channels and selecting the channel with the lower average error rate.

Claim 13

Digital communication apparatus for reducing bit errors in communication of a stream of digital information, comprising one or more connected systems, each system having a processor incorporating an error checking facility in the information, two independent communication channels, a transmitter sending the information incorporating the error checking facility on the two independent communication channels, a receiver receiving the information sent on the two communication channels, and a controller selecting the information received on one or the other of the two channels based on an error checking analysis of the information sent on both of the channels.

Claim 14

Digital communication apparatus for reducing bit errors in communication of a stream of digital information, comprising one or more connected systems, each system having a processor incorporating an error checking facility in the information, two independent communication channels, a transmitter sending the information incorporating the error checking facility on the two independent communication channels, a receiver receiving the information sent on the two communication channels, and a controller selecting the information received on one or the other of the two channels based on an error checking analysis of the information sent on both of the channels.

Claim 15

The apparatus of claim 11 wherein the two channels impose different delays on the communication of the information and further comprising a synchronizer compensating for the different delays prior to the selection of information by the controller.

Claim 16

The apparatus of claim 11 wherein the processor incorporates the error checking facility in the information by organizing the information in blocks of bits and incorporating error correcting information in each of the blocks of bits.

Claim 17

The apparatus of claim 13 wherein the controller selects one of the channels by making a selection for each of the blocks based on an error checking analysis of the error correcting information in the block.

Claim 18

The apparatus of claim 11 wherein the controller in a first system is connected to a processor in a second system, said processor incorporating an error checking facility in the information selected by the controller.

Claim 19

The apparatus of claim 15 wherein the processor adds parity checking bits.

Claim 20

The apparatus of claim 11 wherein the controller selects one of the channels by determining a relative degree of error exhibited in the information sent on the two channels.

Claim 21

The apparatus of claim 17 wherein the controller selects one of the channels for which the information is not in error.

Claim 22

The apparatus of claim 17 wherein the controller selects one of the channels by determining an average error rate over time for each of the channels and selects the channel with the lower average error rate.

Claim 23

Digital communication apparatus for reducing bit errors in communication of a stream of digital information, comprising two or more connected systems, each system having a processor organizing the information in blocks of bits and incorporating error correcting information in each of the blocks of bits, two independent communication channels imposing different delays on the communication of the information, a transmitter sending the information incorporating the error checking facility on the two independent communication channels, a receiver receiving the information sent on the two communication channels, a synchronizer compensating for the different delays imposed by the two channels, and a controller selecting the synchronized information received on one or the other of the two channels by determining a relative degree of error exhibited in the information sent on the two channels, wherein the processor in a first system is connected to a controller in a second system, said processor incorporating an error checking facility in the information selected by the controller.

Claim 24

Digital communication apparatus for reducing bit errors in communication of a stream of digital information, comprising two or more connected systems, each system having a processor organizing the information in blocks of bits and incorporating error correcting information in each of the blocks of bits, two independent communication channels imposing different delays on the communication of the information, a transmitter sending the information incorporating the error checking facility on the two independent communication channels, a receiver receiving the information sent on the two communication channels, a synchronizer compensating for the different delays imposed by the two channels, and a controller selecting the synchronized information received on one or the other of the two channels by determining a relative degree of error exhibited in the information sent on the two channels, wherein the processor in a first system is connected to a controller in a second system, said processor incorporating an error checking facility in the information selected by the controller.