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US5515331A
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DRAM refresh control circuit
Assignee: SK Hynix Inc
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Filing: 1995-01-03
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Granted: 1996-05-07
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Expires: 2015-01-03
Abstract
Abstract A control circuit for refreshing a dynamic random access memory (DRAM) having a plurality of memory cells arranged in rows and columns. The inventive refresh control circuit includes a first circuit for detecting whether a first refresh mode exists in response to row and column address signals applied thereto and for generating a first output signal based on the result of the detection; a second circuit for detecting whether a second refresh mode exists in response to row and column address signals applied thereto and for generating a second output signal based on the result of the detection; a third circuit for detecting whether a reset condition exists in response to row and column address signals applied thereto and for generating a reset signal based on the result of the detection; and a counter circuit, coupled to the first, second, and third detecting circuits, for generating a count value representing a refresh address in response to the first and second output signals and the reset signal.
Inventors
- 👤 Young-Ho Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
145 words
A control circuit for refreshing a dynamic random access memory (DRAM) having a plurality of memory cells arranged in rows and columns, comprising: a first means for detecting a first refresh mode in response to row and column address signals and for generating a first output signal; a second means for detecting a second refresh mode in response to the row and column address signals and for generating a second output signal; a third means for detecting said first refresh mode, said second refresh mode, and a normal mode in response to the row and column address signals and for generating a reset signal in response to the detected modes; and a counter means, coupled to said first, second, and third detecting means, for generating a count value representing a refresh address in response to said first and second output signals and said reset signal.
Claim 2
Dependent Claim
145 words
A control circuit for refreshing a dynamic random access memory (DRAM) having a plurality of memory cells arranged in rows and columns, comprising: a first means for detecting a first refresh mode in response to row and column address signals and for generating a first output signal; a second means for detecting a second refresh mode in response to the row and column address signals and for generating a second output signal; a third means for detecting said first refresh mode, said second refresh mode, and a normal mode in response to the row and column address signals and for generating a reset signal in response to the detected modes; and a counter means, coupled to said first, second, and third detecting means, for generating a count value representing a refresh address in response to said first and second output signals and said reset signal.
Claim 3
Dependent Claim
45 words
The refresh control circuit of claim 1, wherein said reset signal represents an arbitrarily selected value when said row and column address signals include a predetermined sequence of signals and wherein said counter means includes means for setting said count value to said selected value.
Claim 4
Dependent Claim
27 words
The refresh control circuit of claim 1, wherein said counter means includes means for incrementing said count value in response to said first and second output signals.
Claim 5
Dependent Claim
38 words
The refresh control circuit of claim 1, further comprising an OR logic gate between said first and second detecting means and said counter means for generating a clock signal in response to said first and second output signals.
Claim 6
Dependent Claim
156 words
The refresh control circuit of claim 1, wherein said third detecting means includes: a first mode means for detecting said first refresh mode in response to the row and column address signals and for generating a first refresh mode signal; a second mode means for detecting said second refresh mode in response to the row and column address signals and for generating a second refresh mode signal; a normal mode means for detecting said normal mode in response to the row and column address signals and for generating a normal mode signal; one or more flip-flops coupled to said first mode means and said normal mode means for generating a status signal in response to said first refresh mode signal and said normal mode signal; and means, coupled to said one or more flip-flops and said second mode means, for generating said reset signal in response to said status signal and said second refresh mode signal.
Claim 7
Dependent Claim
25 words
The refresh control circuit of claim 4, wherein said counter means includes means for incrementing said counted value in response to said generated clock signal.
Claim 8
Dependent Claim
21 words
The refresh control circuit of claim 5, wherein said one or more flip-flops include at least two flip-flops connected in cascade.
Claim 9
Independent Claim
115 words
A method for controlling the refresh of a dynamic random access memory (DRAM) having a plurality of memory cells arranged in rows and columns, comprising the steps of: detecting a first refresh mode in response to row and column address signals and generating a first output signal; detecting a second refresh mode in response to the row and column address signals and generating a second output signal; detecting said first refresh mode, said second refresh mode, and a normal mode in response to the row and column address signals and generating a reset signal; and counting a value representing a refresh address in accordance with said first and second output signals and said reset signal.
Claim 10
Independent Claim
115 words
A method for controlling the refresh of a dynamic random access memory (DRAM) having a plurality of memory cells arranged in rows and columns, comprising the steps of: detecting a first refresh mode in response to row and column address signals and generating a first output signal; detecting a second refresh mode in response to the row and column address signals and generating a second output signal; detecting said first refresh mode, said second refresh mode, and a normal mode in response to the row and column address signals and generating a reset signal; and counting a value representing a refresh address in accordance with said first and second output signals and said reset signal.
Claim 11
Dependent Claim
20 words
The method of claim 8, wherein said reset signal represents an arbitrarily selected value when said reset condition is detected.
Claim 12
Dependent Claim
24 words
The method of claim 8, wherein said counting step includes setting a counter to an arbitrarily selected value in response to said reset signal.
Claim 13
Dependent Claim
22 words
The method of claim 8, wherein said counting step includes incrementing a counter in response to said first and second output signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-07 | 1999-11-06 | 2000-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-07 | 2003-11-06 | 2004-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-07 | 2007-11-06 | 2008-05-07 | $7700.00 | Window Closed / Lapsed |