Nonvolatile semiconductor memory device having a small number of internal boosting circuits

Claim 2

An electrically erasable programmable nonvolatile memory device comprising: a semiconductor substrate; a memory cell unit, including a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate, a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and a control gate electrode provided on said charge-accumulating layer of said transistor; a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage; a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor; charging means for applying, during a first data-writing period when said bit line is not selected, a first voltage to said control gate electrode and said bit line, and a second voltage to said gate electrode of said select transistor to turn on said select transistor, thereby to charge said drain region to a third voltage lower than the second voltage by the threshold voltage of said select transistor; control-gate voltage switching means for increasing voltages of said source and drain regions and a voltage of a channel region provided between said source and drain regions, thereby to increase the third voltage, by capacitive coupling which occurs between said control gate electrode and said charge-accumulating layer and between said charge-accumulating layer and said source, drain and channel regions when a data-writing high voltage is applied to said control gate during a second data-writing period; and data-write prohibiting means for turning off said select transistor to cut off the current path of said memory cell unit when a source-gate voltage of said select transistor falls below the threshold voltage of said select transistor due to the capacitive coupling.

Claim 3

The device according to claim 1, wherein the first voltage is substantially equal to a power-supply voltage externally applied to said device.

Claim 4

The device according to claim 1, wherein the second voltage is lower than the first voltage and higher than the threshold voltage of said select transistor.

Claim 5

The device according to claim 1, wherein the second voltage is higher than the threshold voltage of said select transistor and is substantially equal to the first voltage.

Claim 6

The device according to claim 1, further comprising voltage-switching means for applying a fourth voltage to said gate electrode of said select transistor during the second data writing period, the fourth voltage being lower than the second voltage and higher than the threshold voltage of said select transistor.

Claim 7

The device according to claim 5, wherein the first voltage and the second voltage are substantially equal to a power-supply voltage externally applied to said device.

Claim 8

An electrically erasable programmable non-volatile memory device comprising: a semiconductor substrate; a memory cell unit, including a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate, a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and a control gate electrode provided on said charge-accumulating layer of said transistor; a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage; a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor; a bit-line charging means for applying, during a data writing period when said bit line is not selected, a first voltage to said bit line, the first voltage being relatively low and higher than the threshold voltage of said select transistor; a gate-voltage applying means for applying, during the data writing period, a second voltage to said gate electrode of said select transistor, the second voltage being higher than the threshold voltage of said select transistor and not exceeding the first voltage; and control-gate voltage switching means for applying a third voltage to said source and drain regions when said memory cell unit is selected, for a predetermined time during the data-writing period, and for applying a high voltage to said control gate after lapse of the predetermined period, the third voltage being lower than the second voltage by at least the threshold voltage of said select transistor.

Claim 9

An electrically erasable programmable non-volatile memory device comprising: a semiconductor substrate; a memory cell unit, including a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate, a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and a control gate electrode provided on said charge-accumulating layer of said transistor; a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage; a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor; a bit-line charging means for applying, during a data writing period when said bit line is not selected, a first voltage to said bit line, the first voltage being relatively low and higher than the threshold voltage of said select transistor; a gate-voltage applying means for applying, during the data writing period, a second voltage to said gate electrode of said select transistor, the second voltage being higher than the threshold voltage of said select transistor and not exceeding the first voltage; and control-gate voltage switching means for applying a third voltage to said source and drain regions when said memory cell unit is selected, for a predetermined time during the data-writing period, and for applying a high voltage to said control gate after lapse of the predetermined period, the third voltage being lower than the second voltage by at least the threshold voltage of said select transistor.

Claim 10

The device according to claim 7, wherein the first voltage is substantially equal to a power-supply voltage externally applied to said device and the third voltage is substantially equal to a ground potential of said device.

Claim 11

The device according to claim 7, wherein the first voltage and the second voltage are substantially equal.

Claim 12

The device according to claim 7, further comprising voltage-switching means for lowering the second voltage after the lapse of the predetermined time during the data-writing period.

Claim 13

The device according to claim 7, wherein gate insulating films having substantially the same thickness are formed between said gate electrode of said select transistor and said semiconductor substrate and between said charge-accumulating layer of said memory cell unit and said semiconductor substrate.

Claim 14

An electrically erasable programmable nonvolatile memory device comprising: a semiconductor substrate; a memory cell unit, including a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate, a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and a control gate electrode provided on said charge-accumulating layer of said transistor; a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage; a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor; charging means for applying, during a first data-writing period when said bit line is not selected, a first voltage to said control gate electrode and said bit line, and a second voltage to said gate electrode of said select transistor to turn on said select transistor, thereby to charge said drain region to a third voltage lower than the second voltage by the threshold voltage of said select transistor; control-gate voltage switching means for increasing voltages of said source and drain regions and a voltage of a channel region provided between said source and drain regions, thereby to increase the third voltage, by capacitive coupling which occurs between said control gate electrode and said charge-accumulating layer and between said charge-accumulating layer and said source, drain and channel regions when a data-writing high voltage is applied to said control gate during a second data-writing period; and data-write prohibiting means for turning off said select transistor to cut off the current path of said memory cell unit when a source-gate voltage of said select transistor falls below the threshold voltage of said select transistor due to the capacitive coupling; and verify means for correcting the threshold voltage, the threshold voltage relating to data writing.

Claim 15

An electrically erasable programmable nonvolatile memory device comprising: a semiconductor substrate; a memory cell unit, including a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate, a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and a control gate electrode provided on said charge-accumulating layer of said transistor; a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage; a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor; charging means for applying, during a first data-writing period when said bit line is not selected, a first voltage to said control gate electrode and said bit line, and a second voltage to said gate electrode of said select transistor to turn on said select transistor, thereby to charge said drain region to a third voltage lower than the second voltage by the threshold voltage of said select transistor; control-gate voltage switching means for increasing voltages of said source and drain regions and a voltage of a channel region provided between said source and drain regions, thereby to increase the third voltage, by capacitive coupling which occurs between said control gate electrode and said charge-accumulating layer and between said charge-accumulating layer and said source, drain and channel regions when a data-writing high voltage is applied to said control gate during a second data-writing period; and data-write prohibiting means for turning off said select transistor to cut off the current path of said memory cell unit when a source-gate voltage of said select transistor falls below the threshold voltage of said select transistor due to the capacitive coupling; and verify means for correcting the threshold voltage, the threshold voltage relating to data writing.

Claim 16

The device according to claim 12, wherein the first voltage is substantially equal to a power-supply voltage externally applied to said device.

Claim 17

The device according to claim 12, wherein the second voltage is lower than the first voltage and higher than the threshold voltage of said select transistor.

Claim 18

The device according to claim 12, wherein the second voltage is higher than the threshold voltage of said select transistor and is substantially equal to the first voltage.

Claim 19

The device according to claim 12, further comprising voltage-switching means for applying a fourth voltage to said gate electrode of said select transistor during the second data-writing period, the fourth voltage being lower than the second voltage and higher than the threshold voltage of said select transistor.

Claim 20

The device according to claim 12, wherein the first voltage and the second voltage are substantially equal to a power-supply voltage externally applied to said device.

Claim 21

An electrically erasable programmable non-volatile memory device comprising: a semiconductor substrate; a memory cell unit, including a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate, a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and a control gate electrode provided on said charge-accumulating layer of said transistor; a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage; a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor; a bit-line charging means for applying, during a data writing period when said bit line is not selected, a first voltage to said bit line, the first voltage being relatively low and higher than the threshold voltage of said select transistor; a gate-voltage applying means for applying, during the data writing period, a second voltage to said gate electrode of said select transistor, the second voltage being higher than the threshold voltage of said select transistor and not exceeding the first voltage; and control-gate voltage switching means for applying a third voltage to said source and drain regions when said memory cell unit is selected, for a predetermined time during the data-writing period, and for applying a high voltage to said control gate after lapse of the predetermined period, the third voltage being lower than the second voltage by at least the threshold voltage of said select transistor; and verify means for correcting the threshold voltage, the threshold voltage relating to data writing.

Claim 22

An electrically erasable programmable non-volatile memory device comprising: a semiconductor substrate; a memory cell unit, including a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate, a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and a control gate electrode provided on said charge-accumulating layer of said transistor; a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage; a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor; a bit-line charging means for applying, during a data writing period when said bit line is not selected, a first voltage to said bit line, the first voltage being relatively low and higher than the threshold voltage of said select transistor; a gate-voltage applying means for applying, during the data writing period, a second voltage to said gate electrode of said select transistor, the second voltage being higher than the threshold voltage of said select transistor and not exceeding the first voltage; and control-gate voltage switching means for applying a third voltage to said source and drain regions when said memory cell unit is selected, for a predetermined time during the data-writing period, and for applying a high voltage to said control gate after lapse of the predetermined period, the third voltage being lower than the second voltage by at least the threshold voltage of said select transistor; and verify means for correcting the threshold voltage, the threshold voltage relating to data writing.

Claim 23

The device according to claim 18, wherein the first voltage is substantially equal to a power-supply voltage externally applied to said device and the third voltage is substantially equal to a ground potential of said device.

Claim 24

The device according to claim 18, wherein the first voltage and the second voltage are substantially equal.

Claim 25

The device according to claim 18, further comprising voltage-switching means for lowering the second voltage after the lapse of the predetermined time during the data-writing period.

Claim 26

The device according to claim 18, wherein said verify means comprises: a flip-flop circuit for determining whether data read from or written into said memory cell unit is in a first state or a second state and holding the determined data in a predetermined holding node; precharge means for precharging said bit line in a verify mode for said memory cell unit; connecting means for connecting said flip-flop circuit to said bit line, said connecting means electrically disconnecting, for a predetermined time period, said bit line from said flip-flop circuit in the verify mode; a first verifying transistor conductive in the verify mode, and a second verifying transistor having a gate controlled in response to a signal from said bit line; and circuit means for forming a current path which allows said first and second transistors to invert dam held by the predetermined holding node of said flip-flop circuit at a termination time of the verify mode.

Claim 27

The device according to claim 22, wherein said flip-flop circuit includes reset means.

Claim 28

The device according to claim 2, wherein the second voltage is lower than the first voltage and higher than the threshold voltage of said select transistor.

Claim 29

The device according to claim 2, wherein the second voltage is higher than the threshold voltage of said select transistor and is substantially equal to the first voltage.

Claim 30

The device according to claim 1, wherein gate insulating films having substantially the same thickness are formed between said gate electrode of said select transistor and said semiconductor substrate and between said charge-accumulating layer of said memory cell unit and said semiconductor substrate.

Claim 31

The device according to claim 8, wherein the first voltage and the second voltage are substantially equal.

Claim 32

The device according to claim 12, wherein said verify means comprises: a flip-flop circuit for determining whether data read from or written into said memory cell unit is in a first state or a second state and holding the determined data in a predetermined holding node; precharge means for precharging said bit line in a verify mode for said memory cell unit; connecting means for connecting said flip-flop circuit to said bit line, said connecting means electrically disconnecting, for a predetermined time period, said bit line from said flip-flop circuit in the verify mode; a first verifying transistor conductive in the verify mode, and a second verifying transistor having a gate controlled in response to a signal from said bit line; and circuit means for forming a current path which allows said first and second transistors to invert data held by the predetermined holding node of said flip-flop circuit at a termination time of the verify mode.

Claim 33

The device according to claim 13, wherein the second voltage is lower than the first voltage and higher than the threshold voltage of said select transistor.

Claim 34

The device according to claim 13, wherein the second voltage is higher than the threshold voltage of said select transistor and is substantially equal to the first voltage.

Claim 35

The device according to claim 19, wherein the first voltage and the second voltage are substantially equal.