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US5515291A Expired / Lapsed US ⏱️ 0.0 years remaining

Apparatus for calculating delay time in logic functional blocks

Assignee: Renesas Electronics Corp
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Filing: 1992-08-14
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Granted: 1996-05-07
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Expires: 2012-08-14
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Abstract

Abstract A delay parameter calculator (13) calculates an input slew rate (tr) as a function of a layout pattern information (D12) to determine delay parameters (K) by substituting the slew rate (tr) for a delay parameter function (K(tr)). An output impedance calculator (15) calculates an impedance (RS) of an accurate output macro cell (21) as a function of a capacitance lumped constant (C) and the delay parameters (K). A delay time calculator (16) solves an equation having the output impedance (RS) as a significant parameter to correctly calculate a delay time (DT) it takes to transmit a signal from an input to an output of a logic functional block composed of MOS transistors.

Inventors

  • 👤 Naoko Omori
  • 👤 Michio Komoda

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 23:39
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3016; G01R31/317; G01R31/31725

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 250 words
An apparatus for calculating a delay time it takes to transmit a signal from an input portion to an output portion of a logic functional block including an MOS transistor, comprising: means for providing an arrangement and wiring result including a layout pattern ranging from said input portion to said output portion of said logic functional block; delay parameter storage means for storing at least one delay parameter which is a function of input slew rate in accordance with various logic functional blocks; an RC lumped constant calculator for calculating an RC lumped constant of an output-side wiring portion of said logic functional block as a function of said arrangement and wiring result; delay parameter determination means for receiving a delay parameter in accordance with said logic functional block as a selected delay parameter from said delay parameter storage means and determining an input slew rate of said logic functional block as a function of said arrangement and wiring result to output an value of said selected delay parameter determined by said input slew rate as a selected delay parameter determined value; output impedance calculation means for calculating an output impedance of said logic functional block from a predetermined output impedance calculation equation as a function of a capacitance of said RC lumped constant and said selected delay parameter determined value; and delay time calculation means for calculating said delay time from a predetermined delay time calculation equation as a function of said RC lumped constant and said output impedance.
Claim 2
Independent Claim 250 words
An apparatus for calculating a delay time it takes to transmit a signal from an input portion to an output portion of a logic functional block including an MOS transistor, comprising: means for providing an arrangement and wiring result including a layout pattern ranging from said input portion to said output portion of said logic functional block; delay parameter storage means for storing at least one delay parameter which is a function of input slew rate in accordance with various logic functional blocks; an RC lumped constant calculator for calculating an RC lumped constant of an output-side wiring portion of said logic functional block as a function of said arrangement and wiring result; delay parameter determination means for receiving a delay parameter in accordance with said logic functional block as a selected delay parameter from said delay parameter storage means and determining an input slew rate of said logic functional block as a function of said arrangement and wiring result to output an value of said selected delay parameter determined by said input slew rate as a selected delay parameter determined value; output impedance calculation means for calculating an output impedance of said logic functional block from a predetermined output impedance calculation equation as a function of a capacitance of said RC lumped constant and said selected delay parameter determined value; and delay time calculation means for calculating said delay time from a predetermined delay time calculation equation as a function of said RC lumped constant and said output impedance.
Claim 3
Dependent Claim 14 words
The apparatus of claim 1, wherein said logic functional block is a CMOS inverter.
Claim 4
Dependent Claim 60 words
The apparatus of claim 1, wherein said predetermined delay time calculation equation is expressed as: ##EQU6## where K0 is said selected delay parameter determined value, C is said capacitance of said RC lumped constant, R is a resistance of said RC lumped constant, β is a threshold voltage coefficient, RS is said output impedance, and DT is said delay time.
Claim 5
Dependent Claim 48 words
The apparatus of claim 3, wherein said predetermined output impedance calculation equation is expressed as: ##EQU7## where K2 and K3 are said selected delay parameter determined values, C is said capacitance of said RC lumped constant, β is said threshold voltage coefficient, and RS is said output impedance.
Claim 6
Dependent Claim 61 words
The apparatus of claim 3, wherein said predetermined output impedance calculation equation is expressed as: ##EQU8## where A1 to A3 are said selected delay parameter determined values, C is said capacitance of said RC lumped constant, β is said threshold voltage coefficient, Ci is a capacitance on an input side of said logic functional block, and RS is said output impedance.

References Cited (Backward Citations)

US4196475A Cited
US4342089A Cited
US4263651A Cited
US4587480A Cited
US4631686A Cited
US4698760A Cited
US4972412A Cited
US5001365A Cited
DE3910507A1 Cited
US5202841A Cited
US5231588A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-05-07 1999-11-06 2000-05-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-05-07 2003-11-06 2004-05-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-05-07 2007-11-06 2008-05-07 $7700.00 Window Closed / Lapsed

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