Interface between SAW filter and Gilbert cell mixer

Claim 2

A modulator, comprising: a) a SAW filter for receiving a signal; b) a Gilbert multiplier which includes i) an input for receiving the signal from the SAW filter; and ii) means for adjusting the impedance of the input.

Claim 3

In a multiplier for a signal, the improvement comprising: a) a SAW filter for delivering the signal; and b) Gilbert multiplier means for receiving the signal at a port i) having an input impedance of less than 200 ohms, and ii) having no significant Miller capacitance.

Claim 4

In a multiplier for a signal, the improvement comprising: a) a SAW filter for delivering the signal; and b) Gilbert multiplier means for receiving the signal at a port i) having an input impedance of less than 200 ohms, and ii) having no significant Miller capacitance.

Claim 5

The combination comprising; a) a Gilbert multiplier which includes a signal input port, and a carrier input port, and b) means for providing, at the signal input port, an input impedance less than 200 ohms.

Claim 6

The combination comprising; a) a Gilbert multiplier which includes a signal input port, and a carrier input port, and b) means for providing, at the signal input port, an input impedance less than 200 ohms.

Claim 7

A modulator, comprising: a) a Surface Acoustic Wave (SAW) filter i) for delivering an information signal; and ii) requiring a load impedance of less than 200 ohms. a) a multiplier which i) has a signal input port which presents an input impedance of less than 200 ohms; i) receives the information signal from the SAW at the input port; and ii) multiplies the information signal by a carrier signal which exceeds 10 MHz.

Claim 8

A modulator, comprising: a) a Surface Acoustic Wave (SAW) filter i) for delivering an information signal; and ii) requiring a load impedance of less than 200 ohms. a) a multiplier which i) has a signal input port which presents an input impedance of less than 200 ohms; i) receives the information signal from the SAW at the input port; and ii) multiplies the information signal by a carrier signal which exceeds 10 MHz.

Claim 9

A modulator, comprising: a) an integrated circuit (IC) which contains a Gilbert multiplier, and which includes a pair of signal input pins; and b) means for causing the pair of signal input pins to present an input impedance of less than 200 ohms.

Claim 10

A modulator, comprising: a) an integrated circuit (IC) which contains a Gilbert multiplier, and which includes a pair of signal input pins; and b) means for causing the pair of signal input pins to present an input impedance of less than 200 ohms.

Claim 11

A modulator, comprising: a) a Gilbert-type multiplier having first and second input ports, for multiplying signals presented to the ports by each other, in which the first port has an input impedance of less than 200 ohms; b) a signal source; c) a Surface Acoustic Wave (SAW) filter connected between the signal source and the first input port; and d) oscillator means, connected to the second input port, for delivering no more than 3.5 milliwatts of power to the second input port.

Claim 12

A modulator, comprising: a) a Gilbert-type multiplier having first and second input ports, for multiplying signals presented to the ports by each other, in which the first port has an input impedance of less than 200 ohms; b) a signal source; c) a Surface Acoustic Wave (SAW) filter connected between the signal source and the first input port; and d) oscillator means, connected to the second input port, for delivering no more than 3.5 milliwatts of power to the second input port.

Claim 13

A mixer which comprises components connected according to the following netlist, which follows SPICE syntax, 1 R1 0, 1 2 R2 0, 2 3 C1 3, 0 4 C2 4, 0 5 Q1 5, 3, 1 6 Q2 6, 4, 2 7 Q3 9, 10, 5 8 Q4 8, 7, 5 9 Q5 9, 7, 6 10 Q6 8, 10, 6. wherein nodes 7 and 10 represent a first input port, nodes 1 and 2 represent a second input port.

Claim 14

A mixer which comprises components connected according to the following netlist, which follows SPICE syntax, 1 R1 0, 1 2 R2 0, 2 3 C1 3, 0 4 C2 4, 0 5 Q1 5, 3, 1 6 Q2 6, 4, 2 7 Q3 9, 10, 5 8 Q4 8, 7, 5 9 Q5 9, 7, 6 10 Q6 8, 10, 6. wherein nodes 7 and 10 represent a first input port, nodes 1 and 2 represent a second input port.

Claim 15

Apparatus according to claim 7 and further comprising a Surface Acoustic Wave (SAW) filter for delivering an information signal to the second port.

Claim 18

For an integrated circuit containing a Gilbert multiplier which has a signal-input stage internally biased in common-emitter mode, the improvement comprising: a) means for converting the signal-input stage to common-base mode.

Claim 19

For an integrated circuit containing a Gilbert multiplier which has a signal-input stage internally biased in common-emitter mode, the improvement comprising: a) means for converting the signal-input stage to common-base mode.

Claim 20

Apparatus according to claim 10, and further comprising b) a signal source for providing a signal to the signal-input stage; and c) a surface acoustic wave filter for filtering the signal prior to reaching the signal-input stage.

Claim 21

For an integrated circuit (IC) comprising a Gilbert multiplier, and including the following components: A) a pair of signal input pins, connected to respective bases of first and second BJTs, which are connected within the IC in common-emitter mode; C) a pair of GAIN ADJUST pins, connected to respective emitters of said BJTs; D) a BIAS pin connected to bases of third and fourth BJTs, which receive current from the first and second BJTs; and E) an emitter power supply pin (V EE ), the improvement comprising: a) means for grounding the BIAS pin, b) means for creating a pair of signal shorts, each between a respective signal pin and ground, c) means for applying a signal to the GAIN ADJUST pins, d) means for turning off the third and fourth BJTs, to thereby bias the first and second BJT's in common-base mode.

Claim 22

For an integrated circuit (IC) comprising a Gilbert multiplier, and including the following components: A) a pair of signal input pins, connected to respective bases of first and second BJTs, which are connected within the IC in common-emitter mode; C) a pair of GAIN ADJUST pins, connected to respective emitters of said BJTs; D) a BIAS pin connected to bases of third and fourth BJTs, which receive current from the first and second BJTs; and E) an emitter power supply pin (V EE ), the improvement comprising: a) means for grounding the BIAS pin, b) means for creating a pair of signal shorts, each between a respective signal pin and ground, c) means for applying a signal to the GAIN ADJUST pins, d) means for turning off the third and fourth BJTs, to thereby bias the first and second BJT's in common-base mode.