Patent US5515012A successfully refreshed from Google Patents.
US5515012A
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US
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Very low noise, wide frequency range phase lock loop
Assignee: Philips Semiconductors Inc
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Filing: 1995-05-17
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Granted: 1996-05-07
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Expires: 2015-05-17
Abstract
Abstract A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN -- terminal. The drain terminal of MOS transistor M4 provides an OUT -- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.
Inventors
- 👤 Bharat Bhushan
- 👤 Christopher G. Arcus
- 👤 Paul D. Ta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:46
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03K; H03K3/00; H03K3/02; H03K3/023; H03K3/0231; H03K3/027; H03K3/03; H03K3/0315; H03K3/0322
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
393 words
An amplifier stage for a ring-style, multi-stage VCO of a phase lock loop circuit , comprising: an input terminal for receiving a control voltage; a lowpass filter connected between the input terminal and a first reference voltage; a voltage to current converter stage including: a first MOS transistor M1 of a first type having a gate terminal connected to the input terminal, having a source terminal connected through a resistor R1 to the first reference voltage, and having a drain terminal; a second diode-connected MOS transistor M2 of a second type having a drain terminal and a gate terminal connected together and to the drain terminal of the first MOS transistor M1, and having a source terminal connected to a second reference voltage; a differential amplifier stage including: a current-source MOS transistor M10 of the second type having a source terminal connected to the second reference voltage, having a gate terminal connected to the drain of the first MOS transistor M1, and having a drain terminal; a pair of MOS transistors M4 and M5 of the first type having source terminals connected together and to the drain terminal of the current-source MOS transistor M10, wherein a gate terminal of MOS transistor M4 is designated as an IN terminal, wherein a gate terminal of MOS transistor M5 is designated as an IN -- terminal, wherein a drain terminal of MOS transistor M4 provides an OUT -- signal for the differential amplifier stage, and wherein a drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage; a MOS transistor M6 of the first type, forming a load impedance for MOS transistor M4, wherein a drain terminal of MOS transistor M6 is connected to a drain terminal of MOS transistor M4, wherein a source terminal of MOS transistor M6 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M6 is connected to the input terminal of the amplifier stage; a MOS transistor M7 of the first type, forming a load impedance for MOS transistor M5, wherein a drain terminal of MOS transistor M7 is connected to a drain terminal of MOS transistor M5, wherein a source terminal of MOS transistor M7 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M7 is connected to the input terminal of the amplifier stage.
Claim 2
Dependent Claim
393 words
An amplifier stage for a ring-style, multi-stage VCO of a phase lock loop circuit , comprising: an input terminal for receiving a control voltage; a lowpass filter connected between the input terminal and a first reference voltage; a voltage to current converter stage including: a first MOS transistor M1 of a first type having a gate terminal connected to the input terminal, having a source terminal connected through a resistor R1 to the first reference voltage, and having a drain terminal; a second diode-connected MOS transistor M2 of a second type having a drain terminal and a gate terminal connected together and to the drain terminal of the first MOS transistor M1, and having a source terminal connected to a second reference voltage; a differential amplifier stage including: a current-source MOS transistor M10 of the second type having a source terminal connected to the second reference voltage, having a gate terminal connected to the drain of the first MOS transistor M1, and having a drain terminal; a pair of MOS transistors M4 and M5 of the first type having source terminals connected together and to the drain terminal of the current-source MOS transistor M10, wherein a gate terminal of MOS transistor M4 is designated as an IN terminal, wherein a gate terminal of MOS transistor M5 is designated as an IN -- terminal, wherein a drain terminal of MOS transistor M4 provides an OUT -- signal for the differential amplifier stage, and wherein a drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage; a MOS transistor M6 of the first type, forming a load impedance for MOS transistor M4, wherein a drain terminal of MOS transistor M6 is connected to a drain terminal of MOS transistor M4, wherein a source terminal of MOS transistor M6 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M6 is connected to the input terminal of the amplifier stage; a MOS transistor M7 of the first type, forming a load impedance for MOS transistor M5, wherein a drain terminal of MOS transistor M7 is connected to a drain terminal of MOS transistor M5, wherein a source terminal of MOS transistor M7 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M7 is connected to the input terminal of the amplifier stage.
Claim 3
Dependent Claim
29 words
The amplifier stage of claim 1 wherein the first type of MOS transistor is an NMOS type and wherein the second type of MOS transistor is a PMOS type.
Claim 4
Dependent Claim
479 words
A phase lock loop circuit, comprising: a reference signal input terminal; a phase/frequency detector circuit, which has a first input terminal connected to the reference signal input terminal, which has a second input terminal, and which has an output terminal for providing a control voltage; a lowpass filter circuit connected to the output terminal of the phase/frequency detector circuit; a voltage-to-current converter stage which has an input terminal connected to the lowpass filter circuit, and which has an output terminal providing an output current proportional to the control voltage; said voltage-to-current converter including: a first MOS transistor M1 of a first type having a gate terminal connected to the low-pass filter circuit, having a source terminal connected through a resistor R1 to a first reference voltage, and having a drain terminal; a second diode-connected MOS transistor M2 of a second type having a drain terminal and a gate terminal connected together and to the drain terminal of the first MOS transistor M1, and having a source terminal connected to a second reference voltage; two or more differential amplifier stages, each stage including: a current-source MOS transistor M10 of the second type having a source terminal connected to the second reference voltage, having a gate terminal connected to the drain of the first MOS transistor M1, and having a drain terminal; a pair of MOS transistors M4 and M5 of the first type having source terminals connected together and to the drain terminal of the current-source MOS transistor M10, wherein a gate terminal of MOS transistor M4 is designated as an IN terminal, wherein a gate terminal of MOS transistor M5 is designated as an IN -- terminal, wherein a drain terminal OUT -- of MOS transistor M4 provides an OUT -- signal for the differential amplifier stage, and wherein a drain terminal OUT of MOS transistor M5 provides an OUT signal for the differential amplifier stage; a MOS transistor M6 of the first type, forming a load impedance for MOS transistor M4, wherein a drain terminal of MOS transistor M6 is connected to a drain terminal of MOS transistor M4, wherein a source terminal of MOS transistor M6 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M6 is connected to the reference signal input terminal; a MOS transistor M7 of the first type, forming a load impedance for MOS transistor M5, wherein a drain terminal of MOS transistor M7 is connected to a drain terminal of MOS transistor M5, wherein a source terminal of MOS transistor M7 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M7 is connected to the reference signal input terminal; wherein the IN terminals and the IN -- terminals of each stage are connected to OUT and OUT -- terminals of another stage to provide a VCO for the phase lock loop circuit.
Claim 5
Dependent Claim
479 words
A phase lock loop circuit, comprising: a reference signal input terminal; a phase/frequency detector circuit, which has a first input terminal connected to the reference signal input terminal, which has a second input terminal, and which has an output terminal for providing a control voltage; a lowpass filter circuit connected to the output terminal of the phase/frequency detector circuit; a voltage-to-current converter stage which has an input terminal connected to the lowpass filter circuit, and which has an output terminal providing an output current proportional to the control voltage; said voltage-to-current converter including: a first MOS transistor M1 of a first type having a gate terminal connected to the low-pass filter circuit, having a source terminal connected through a resistor R1 to a first reference voltage, and having a drain terminal; a second diode-connected MOS transistor M2 of a second type having a drain terminal and a gate terminal connected together and to the drain terminal of the first MOS transistor M1, and having a source terminal connected to a second reference voltage; two or more differential amplifier stages, each stage including: a current-source MOS transistor M10 of the second type having a source terminal connected to the second reference voltage, having a gate terminal connected to the drain of the first MOS transistor M1, and having a drain terminal; a pair of MOS transistors M4 and M5 of the first type having source terminals connected together and to the drain terminal of the current-source MOS transistor M10, wherein a gate terminal of MOS transistor M4 is designated as an IN terminal, wherein a gate terminal of MOS transistor M5 is designated as an IN -- terminal, wherein a drain terminal OUT -- of MOS transistor M4 provides an OUT -- signal for the differential amplifier stage, and wherein a drain terminal OUT of MOS transistor M5 provides an OUT signal for the differential amplifier stage; a MOS transistor M6 of the first type, forming a load impedance for MOS transistor M4, wherein a drain terminal of MOS transistor M6 is connected to a drain terminal of MOS transistor M4, wherein a source terminal of MOS transistor M6 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M6 is connected to the reference signal input terminal; a MOS transistor M7 of the first type, forming a load impedance for MOS transistor M5, wherein a drain terminal of MOS transistor M7 is connected to a drain terminal of MOS transistor M5, wherein a source terminal of MOS transistor M7 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M7 is connected to the reference signal input terminal; wherein the IN terminals and the IN -- terminals of each stage are connected to OUT and OUT -- terminals of another stage to provide a VCO for the phase lock loop circuit.
Claim 6
Dependent Claim
31 words
The phase lock loop circuit of claim 3 wherein the first type of MOS transistor is an NMOS type and wherein the second type of MOS transistor is a PMOS type.
References Cited (Backward Citations)
US5285173A
Cited
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| 3.5 Years (Year 4) | 1999-05-07 | 1999-11-06 | 2000-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-07 | 2003-11-06 | 2004-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-07 | 2007-11-06 | 2008-05-07 | $7700.00 | Window Closed / Lapsed |