Method of testing cache memories used for an information processing apparatus

Claim 1

A cache memory test method for an information processing apparatus including a main memory, a plurality of cache memories which have different memory capacities and are accessed at the same time when said main memory is accessed, and a determining circuit for, when data is read out from said main memory, determining a cache hit indicating that the data is read out from one of said cache memories, or a cache mishit indicating that the data is not read out from any one of said cache memories, comprising: a first step of setting data for testing said cache memories in said main memory such that data values of the data have regularity; a second step of loading the data from said main memory into each of said cache memories, the data being not less in amount than the capacity of each of said cache memories; a third step of recording information indicating a cache hit indicating that the data is read out from one of said cache memories when said main memory is accessed to read out the data therefrom, or information indicating a cache mishit indicating that the data is not read out from any one of said cache memories, thereby forming a cache hit/mishit information table; a fourth step of determining a normal/abnormal condition of each of said cache memories from a state of occurrence of cache hits and cache mishits indicated by the cache hit/mishit information table; a fifth step of determining a normal/abnormal condition of each of said cache memories by checking, on the basis of the regularity, correctness of a data value with respect to data for which a cache hit is determined in the third step; and a sixth step of determining the capacity of each of said cache memories on the basis of an amount of data for which cache hits are determined in the third step.