Patent US5513189A successfully refreshed from Google Patents.
US5513189A
Expired / Lapsed
US
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Boundary scan system with improved error reporting using sentinel bit patterns
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-05-25
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Granted: 1996-04-30
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Expires: 2014-05-25
Abstract
Abstract A boundary scan bus error reporting circuitry loads an unused sentinel bit pattern into the boundary scan instruction register in a conventional error reporting boundary scan test system. The unused sentinel bit pattern signifies that a fault exists somewhere upstream of the instruction register in the boundary scan circuitry associated with a specific integrated circuit. The special sentinel pattern is loaded into the instruction register in response to an illegal instruction control signal generated by an instruction decoder coupled to the instruction latch in the boundary scan architecture.
Inventors
- 👤 Thomas W. Savage
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:35
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
145 words
An integrated circuit, comprising: a plurality of external device terminals; a plurality of core logic elements; a boundary scan test access port; a boundary scan instruction register, formed of a plurality of boundary scan cells and coupled to said device terminals and said core logic elements, for receiving instructions from an externally located initiator; said boundary scan test access port including a test data input terminal, a test data output terminal, a test clock terminal and a test mode select terminal; means coupled to said boundary scan instruction register for detecting receipt of an illegal instruction; and loading means responsive to said detecting means for loading standard sentinel bits into said boundary scan instruction register when no illegal instruction is detected and for loading a different plurality of sentinel bits to said boundary scan instruction register in response to the detection of an illegal instruction.
Claim 2
Dependent Claim
145 words
An integrated circuit, comprising: a plurality of external device terminals; a plurality of core logic elements; a boundary scan test access port; a boundary scan instruction register, formed of a plurality of boundary scan cells and coupled to said device terminals and said core logic elements, for receiving instructions from an externally located initiator; said boundary scan test access port including a test data input terminal, a test data output terminal, a test clock terminal and a test mode select terminal; means coupled to said boundary scan instruction register for detecting receipt of an illegal instruction; and loading means responsive to said detecting means for loading standard sentinel bits into said boundary scan instruction register when no illegal instruction is detected and for loading a different plurality of sentinel bits to said boundary scan instruction register in response to the detection of an illegal instruction.
Claim 3
Dependent Claim
38 words
The invention of claim 1 wherein said loading means includes multiplexer means having a pair of inputs coupled, respectively, to a source of said standard sentinel bits and to a source of said different plurality of sentinel bits.
Claim 4
Dependent Claim
132 words
An integrated circuit for use in a chained serial bus, comprising: a plurality of core logic elements; a boundary scan instruction register connected to at least one of the plurality of core logic elements; a test data in terminal for inputting an instruction into the boundary scan instruction register; a decoder for detecting an error in the instruction in the boundary scan instruction register and for outputting a signal indicating that the error was detected; and means, responsive to the signal output from the decoder, for loading a first predetermined pattern of sentinel bits into the boundary scan instruction register when no error is detected by the decoder and for loading a second predetermined pattern of sentinel bits into the boundary scan instruction register when an error is detected by the decoder.
Claim 5
Dependent Claim
132 words
An integrated circuit for use in a chained serial bus, comprising: a plurality of core logic elements; a boundary scan instruction register connected to at least one of the plurality of core logic elements; a test data in terminal for inputting an instruction into the boundary scan instruction register; a decoder for detecting an error in the instruction in the boundary scan instruction register and for outputting a signal indicating that the error was detected; and means, responsive to the signal output from the decoder, for loading a first predetermined pattern of sentinel bits into the boundary scan instruction register when no error is detected by the decoder and for loading a second predetermined pattern of sentinel bits into the boundary scan instruction register when an error is detected by the decoder.
Claim 6
Dependent Claim
26 words
The integrated circuit of claim 3, further comprising means for outputting data in the boundary scan instruction register, including the sentinel bits, from the integrated circuit.
Claim 7
Dependent Claim
28 words
The integrated circuit of claim 3, wherein the contents of the first and second predetermined pattern of sentinel bits indicate a first and a second error condition, respectively.
Claim 8
Dependent Claim
49 words
The integrated circuit of claim 3, wherein the location of the sentinel bits within the boundary scan instruction register indicates that the error has occurred within the integrated circuit and, wherein other integrated circuits in the chained serial bus indicate errors by replacing different portions of the sentinel bits.
Claim 9
Independent Claim
83 words
A method for indicating an error upstream of an integrated circuit in a serial bus, comprising the steps of; inputting an instruction to a boundary scan instruction register; examining the instruction to determine if the instruction is valid or invalid; inserting a first predetermined sentinel bit pattern in a portion of the boundary scan instruction register when the instruction is valid; and inserting a second predetermined sentinel bit pattern in the portion of the boundary scan instruction register when the instruction is invalid.
Claim 10
Independent Claim
83 words
A method for indicating an error upstream of an integrated circuit in a serial bus, comprising the steps of; inputting an instruction to a boundary scan instruction register; examining the instruction to determine if the instruction is valid or invalid; inserting a first predetermined sentinel bit pattern in a portion of the boundary scan instruction register when the instruction is valid; and inserting a second predetermined sentinel bit pattern in the portion of the boundary scan instruction register when the instruction is invalid.
Claim 11
Dependent Claim
26 words
The method of claim 7, further including the step of outputting data, including the sentinel bits, in the boundary scan instruction register from the integrated circuit.
Claim 12
Dependent Claim
33 words
The method of claim 8, further including the step of determining that an error occurred upstream of the boundary scan instruction register when the sentinel bits include the second predetermined sentinel bit pattern.
Claim 13
Dependent Claim
123 words
An integrated circuit for use in a serial bus, comprising: at least one core logic element; a boundary scan instruction register connected to the at least one core logic element; a test data in terminal for inputting an instruction register; a decoder for checking for an error in the boundary scan instruction register and for outputting a signal indicating whether the error was detected; and means, responsive to the signal output from the decoder, for altering the bit pattern of the boundary scan instruction register when at least one predetermined error condition occurs, wherein the predetermined error condition is one of a condition where an error is detected by the decoder and a condition where an error is not detected by the decoder.
Claim 14
Dependent Claim
123 words
An integrated circuit for use in a serial bus, comprising: at least one core logic element; a boundary scan instruction register connected to the at least one core logic element; a test data in terminal for inputting an instruction register; a decoder for checking for an error in the boundary scan instruction register and for outputting a signal indicating whether the error was detected; and means, responsive to the signal output from the decoder, for altering the bit pattern of the boundary scan instruction register when at least one predetermined error condition occurs, wherein the predetermined error condition is one of a condition where an error is detected by the decoder and a condition where an error is not detected by the decoder.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-30 | 1999-10-30 | 2000-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-30 | 2003-10-30 | 2004-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-30 | 2007-10-30 | 2008-04-30 | $7700.00 | Window Closed / Lapsed |