US5513143A
Expired / Lapsed
US
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Data cache memory internal circuitry for reducing wait states
Assignee: STMicroelectronics lnc USA
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Filing: 1992-07-31
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Granted: 1996-04-30
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Expires: 2012-07-31
Abstract
Abstract The mechanism for performing writes to the data cache memory in a cache subsystem is modified to reduce the occurrence of microprocessor wait states. Concurrently, with operation of the tag RAM, the write signal from the microprocessor propagates through the data cache up to a point in the internal circuitry of the data cache which is as close as reasonably possible to the memory cell being written. At this point in the circuitry, the write signal is gated by the Match signal from the tag RAM. Address decoding is completed prior to receiving the Match signal, such that when the tag RAM generates a "hit" Match output signal, the write signal is allowed to finish propagating through data cache internal circuitry without additional address set-up time. This allows the memory cell to be written to quickly and reduces the probability of microprocessor wait states. In a preferred embodiment of the present invention, the write signal propagates to a logic function, such as a logic gate, where it is gated by the Match signal from the tag RAM and data. When the tag RAM generates a "hit" Match output signal, the write signal as well as the data is allowed to finish propagating to the memory cell.
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:45
CPC Classifications
G; G11; G11C; G11C15/00; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/00; G11C7/10; G11C7/1078
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
160 words
A data cache memory, comprising: a memory matrix of the data cache memory which stores a data of the data cache memory, wherein said memory matrix has a plurality of rows and columns and a plurality of memory cells; a decode logic coupled to said memory matrix which provides decoding ability for the plurality of rows and columns of said memory matrix; a plurality of data input-output buffers coupled to said memory matrix through which the data is written to or read from said memory matrix thus providing the data cache memory with an interface ability; a write driver circuitry, connected to said decode logic, having a write input signal, a match input signal, and a data input signal, wherein the write driver circuitry allows the data cache memory to interface with an external circuitry; and means, included in said write driver circuitry, for preventing completion of a write cycle from a microprocessor until a valid match signal is received.
Claim 2
Dependent Claim
160 words
A data cache memory, comprising: a memory matrix of the data cache memory which stores a data of the data cache memory, wherein said memory matrix has a plurality of rows and columns and a plurality of memory cells; a decode logic coupled to said memory matrix which provides decoding ability for the plurality of rows and columns of said memory matrix; a plurality of data input-output buffers coupled to said memory matrix through which the data is written to or read from said memory matrix thus providing the data cache memory with an interface ability; a write driver circuitry, connected to said decode logic, having a write input signal, a match input signal, and a data input signal, wherein the write driver circuitry allows the data cache memory to interface with an external circuitry; and means, included in said write driver circuitry, for preventing completion of a write cycle from a microprocessor until a valid match signal is received.
Claim 3
Dependent Claim
61 words
The data cache memory of claim 1, where said preventing means only allows said write input signal of said write cycle to propagate to a logic gate of said data cache memory until said valid match signal is received, wherein said logic gate is in close proximity to a memory cell of the plurality of memory cells of said memory matrix.
Claim 4
Dependent Claim
33 words
The data cache memory of claim 2, wherein said write input signal will be allowed to propagate to the memory cell to write said memory cell when said valid match signal is received.
Claim 5
Dependent Claim
34 words
The data cache memory of claim 3, wherein said preventing means is a gating logic internal to said data cache memory with said match input signal and said write input signal as input signals.
Claim 6
Dependent Claim
39 words
The data cache memory of claim 4, wherein said gating logic allows said write input signal to only propagate to said logic gate of said data cache memory when said match input signal is at a specific logic level.
Claim 7
Dependent Claim
38 words
The data cache memory of claim 3, wherein said preventing means is a gating logic internal to said data cache memory with said match input signal, said write input signal, and said data input signal as input signals.
Claim 8
Dependent Claim
39 words
The data cache memory of claim 6, where said gating logic allows said write input signal to only propagate to said logic gate of said data cache memory when said match input signal is at a specific logic level.
Claim 9
Dependent Claim
21 words
The data cache memory of claim 7, wherein the specific logic level of said match input signal is a logic low.
Claim 10
Dependent Claim
51 words
The data cache memory of claim 7, wherein said gating logic is a NAND gate with said match input signal, said write input signal and said data input signal as input signals of said NAND gate, and said NAND gate has an output signal which is connected to said decode logic.
Claim 11
Dependent Claim
45 words
The data cache memory of claim 7, wherein said gating logic allows said write input signal to finish propagation to reach said memory cell when said data input signal, said write input signal, and said match input signal are equal to a predetermined logic level.
Claim 12
Dependent Claim
16 words
The data cache memory of claim 10, wherein said predetermined logic level is a logic high.
Claim 13
Dependent Claim
27 words
The data cache memory of claim 1, wherein a memory cell of the plurality of memory cells is connected to said decode logic via bitlines and wordlines.
Claim 14
Independent Claim
73 words
A method for writing data to a memory array of a data cache memory, comprising the steps of: decoding an input address; selecting a row of the memory array of the data cache memory corresponding to the decoded address; preventing a data from being written into said memory array while the input address is being decoded; and upon receipt of a control signal, enabling the data to be written into the memory array.
Claim 15
Independent Claim
73 words
A method for writing data to a memory array of a data cache memory, comprising the steps of: decoding an input address; selecting a row of the memory array of the data cache memory corresponding to the decoded address; preventing a data from being written into said memory array while the input address is being decoded; and upon receipt of a control signal, enabling the data to be written into the memory array.
Claim 16
Dependent Claim
37 words
The method of claim 13, wherein the control signal is a match signal generated by a cache tag memory and the data is written to the memory array only when the control signal indicates a cache hit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-30 | 1999-10-30 | 2000-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-30 | 2003-10-30 | 2004-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-30 | 2007-10-30 | 2008-04-30 | $7700.00 | Window Closed / Lapsed |