US5510848A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for receiving and decoding digital signals in accordance with two image definition levels
Assignee: US Philips Corp
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Filing: 1994-06-30
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Granted: 1996-04-23
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Expires: 2014-06-30
Abstract
Abstract A system for receiving and decoding digital signals in accordance with two image definition levels. The system includes a transmission channel decoding sub-assembly; a source decoding sub-assembly for decoding signals of a higher definition level or signals of a lower definition level; a device for displaying the decoded signals available at the output of this sub-assembly; at a second output of the sub-assembly, a device for detecting errors during source decoding, followed, in series, by a decision circuit for controlling the switch in accordance with the output signal of said error detection device, as well as for controlling the change-over of the decoding sub-assembly from one of the two source decoding modes to the other.
Inventors
- 👤 Gilles Nocture
- 👤 Thierry Fautier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:16
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/40; H04N21/43; H04N21/44; H04N19/00; H04N19/85; H04N19/89; H04N21/20; H04N21/23; H04N21/234; H04N21/2343; H04N21/23439; H04N21/236; H04N21/2365; H04N21/41; H04N21/426; H04N21/434; H04N21/4347; H04N21/44016; H04N21/442; H04N21/44209
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
205 words
A system for receiving and decoding digital signals having two image definition levels, a higher image definition level and a lower image definition level, the system comprising: a) a sub-assembly for receiving the digital signals and including i) a first channel decoder for decoding signals of the higher definition level ii) a second channel decoder for decoding signals of the lower definition level, said first and second channel decoders being coupled in parallel and iii) a switch coupled to the first and second channel decoders for selecting one of said channel decoders; b) a source decoding sub-assembly for decoding the signals from the selected channel decoder and being arranged to decode both the higher and the lower definition levels; c) an error detector coupled to the source decoding sub-assembly for detecting perturbations in the received digital signals and for providing an output signal which indicates the level of perturbations in the received signals; and d) a decision circuit coupled to the error detector for controlling the switch in accordance with the output signal and for controlling the source decoding sub-assembly to decode the higher definition level if the first channel decoder is selected and the lower definition level if the second channel decoder is selected.
Claim 2
Independent Claim
205 words
A system for receiving and decoding digital signals having two image definition levels, a higher image definition level and a lower image definition level, the system comprising: a) a sub-assembly for receiving the digital signals and including i) a first channel decoder for decoding signals of the higher definition level ii) a second channel decoder for decoding signals of the lower definition level, said first and second channel decoders being coupled in parallel and iii) a switch coupled to the first and second channel decoders for selecting one of said channel decoders; b) a source decoding sub-assembly for decoding the signals from the selected channel decoder and being arranged to decode both the higher and the lower definition levels; c) an error detector coupled to the source decoding sub-assembly for detecting perturbations in the received digital signals and for providing an output signal which indicates the level of perturbations in the received signals; and d) a decision circuit coupled to the error detector for controlling the switch in accordance with the output signal and for controlling the source decoding sub-assembly to decode the higher definition level if the first channel decoder is selected and the lower definition level if the second channel decoder is selected.
Claim 3
Dependent Claim
36 words
A system as claimed in claim 1, further including a demultiplexer coupled between said sub-assembly for decoding and said source decoding sub-assembly, said demultiplexer for demultiplexing a plurality of signal sequences having a similar definition level.
Claim 4
Dependent Claim
26 words
A system as claimed in claim 2, further including a second error detector coupled to the demultiplexer and the decision circuit for detecting errors during demultiplexing.
Claim 5
Dependent Claim
36 words
A system as claimed in claim 3, further including a third error detector, coupled to the sub-assembly for decoding and to the decision circuit for detecting errors in the decoding performed by the sub-assembly for decoding.
Claim 6
Dependent Claim
27 words
A system as claimed in claim 1, further including an inverse control device for inverse control of the switch by returning the switch to its previous state.
Claim 7
Dependent Claim
21 words
A system as claimed in claim 1, further including a device for displaying the decoded signals of said source decoding sub-assembly.
Claim 8
Independent Claim
191 words
A system for receiving and decoding digital signals having two image definition levels, a higher image definition level and a lower image definition level, the system comprising: a) a sub-assembly for receiving the digital signals and including i) a first channel decoder for decoding signals of the higher definition level, ii) a second channel decoder for decoding signals of the lower definition level, said first and second channel decoders being coupled in parallel, and iii) a switch coupled to the first and second channel decoders for selecting one of said channel decoders; b) a source decoding sub-assembly for decoding the signals from the selected channel decoder and being arranged to decode both the higher and the lower definition levels; c) an error detector coupled to the source decoding sub-assembly for detecting perturbations in the received digital signals and for providing an output signal which indicates the level of perturbations in the received signals; and d) a decision circuit coupled to the error detector for controlling the switch in accordance with the output signal such that if the output signal indicates a high perturbation level the switch selects the second channel decoder.
Claim 9
Independent Claim
191 words
A system for receiving and decoding digital signals having two image definition levels, a higher image definition level and a lower image definition level, the system comprising: a) a sub-assembly for receiving the digital signals and including i) a first channel decoder for decoding signals of the higher definition level, ii) a second channel decoder for decoding signals of the lower definition level, said first and second channel decoders being coupled in parallel, and iii) a switch coupled to the first and second channel decoders for selecting one of said channel decoders; b) a source decoding sub-assembly for decoding the signals from the selected channel decoder and being arranged to decode both the higher and the lower definition levels; c) an error detector coupled to the source decoding sub-assembly for detecting perturbations in the received digital signals and for providing an output signal which indicates the level of perturbations in the received signals; and d) a decision circuit coupled to the error detector for controlling the switch in accordance with the output signal such that if the output signal indicates a high perturbation level the switch selects the second channel decoder.
Claim 10
Dependent Claim
21 words
A system as claimed in claim 7, further including a device for displaying the decoded signals of said source decoding sub-assembly.
Claim 11
Dependent Claim
29 words
A system as claimed in claim 7, wherein the error detector measures the number of perturbed pictures in a sequence N of successive pictures to determine the perturbation level.
Claim 12
Dependent Claim
60 words
A system as claimed in claim 7, wherein the source decoding sub-assembly includes two modes of operation a high definition signal decoding mode and a low definition signal decoding mode and wherein the decision circuit outputs a signal to the source decoding sub-assembly indicating which mode should be selected by the source decoding sub-assembly in dependence on the perturbation level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-23 | 1999-10-23 | 2000-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-23 | 2003-10-23 | 2004-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-23 | 2007-10-23 | 2008-04-23 | $7700.00 | Window Closed / Lapsed |