US5509013A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiplexer control system
Assignee: Fujitsu Ltd
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Filing: 1994-03-30
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Granted: 1996-04-16
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Expires: 2014-03-30
Abstract
Abstract A multiplexer control system is used to control multiplexing of data of a plurality of channels including channels having different transmission speeds. The multiplexer control system includes a bit map memory storing, in a bit map format, bits indicating existence of output timings respectively corresponding to different transmission speeds, a rate setting memory in which identification numbers indicating the transmission speeds are set in correspondence with the channels, and a controlling part for outputting an output timing signal depending on the transmission speed of the corresponding channel, based on the bit which indicates the existence of the output timing and is read by making access to the bit map memory and the identification number read by making access to the rate setting memory. The output timing signal determines the multiplexing of the data of the plurality of channels.
Inventors
- 👤 Makoto Adachi
- 👤 Tetsuo Tachibana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:46
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04J; H04J3/00; H04J3/16; H04J3/1605; H04J3/1623; H04J3/1647; H04J3/1682; H04J3/22; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5672
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
154 words
A multiplexer control system for controlling multiplexing of input data of a plurality of channels including channels having different transmission speeds, said multiplexer control system comprising: a bit map memory having addresses storing, in a bit map format, bits indicating output timings respectively corresponding to different transmission speeds; a rate setting memory having addresses at which identification numbers indicating the different transmission speeds are set in correspondence with said channels; and controlling means for outputting an output timing signal depending on the transmission speed of a corresponding channel, based on a bit which indicates the output timing of the corresponding channel and the identification number which indicates the transmission speed of the corresponding channel, said controlling means reading said bit and said identification number by respectively making access to said bit map memory and said rate setting memory, said output timing signal determining the multiplexing of the input data of the plurality of channels.
Claim 2
Dependent Claim
154 words
A multiplexer control system for controlling multiplexing of input data of a plurality of channels including channels having different transmission speeds, said multiplexer control system comprising: a bit map memory having addresses storing, in a bit map format, bits indicating output timings respectively corresponding to different transmission speeds; a rate setting memory having addresses at which identification numbers indicating the different transmission speeds are set in correspondence with said channels; and controlling means for outputting an output timing signal depending on the transmission speed of a corresponding channel, based on a bit which indicates the output timing of the corresponding channel and the identification number which indicates the transmission speed of the corresponding channel, said controlling means reading said bit and said identification number by respectively making access to said bit map memory and said rate setting memory, said output timing signal determining the multiplexing of the input data of the plurality of channels.
Claim 3
Dependent Claim
38 words
The multiplexer control system as claimed in claim 1, which further comprises a multiplexer, coupled to said controlling means, multiplexing the input data of the plurality of channels based on the output timing signal from said controlling means.
Claim 4
Dependent Claim
110 words
The multiplexer control system as claimed in claim 1, wherein said bit map memory includes a number of addresses depending on a ratio of a maximum transmission speed and a minimum transmission speed of said channels, each of said addresses having a bit configuration corresponding to the transmission speeds, said bit map memory storing with respect to the maximum transmission speed a bit-indicating that the output timing exists at all of the addresses and storing with respect to other transmission speeds the bit indicating that the output timing exists at each address depending on a ratio of each of said other transmission speeds with respect to the maximum transmission speed.
Claim 5
Dependent Claim
56 words
The multiplexer control system as claimed in claim 1, wherein said controlling means reads, from successively increasing addresses of said bit map memory, a bit string indicating the output timings and latches the read bit string, and reads from addresses corresponding to the channels of said rate setting memory the identification numbers indicating the transmission speeds.
Claim 6
Dependent Claim
70 words
The multiplexer control system as claimed in claim 4, wherein said controlling means comprises: means for decoding the identification number read from said rate setting memory to obtain a decoded identification number; means for selecting one bit from the bit string indicating the output timings based on the decoded identification number; and means for outputting the output timing signal when the selected one bit indicates that the output timing exists.
Claim 7
Dependent Claim
38 words
The multiplexer control system as claimed in claim 5, which further comprises a multiplexer, coupled to said controlling means, multiplexing the input data of the plurality of channels based on the output timing signals from said controlling means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-16 | 1999-10-16 | 2000-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-16 | 2003-10-16 | 2004-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-16 | 2007-10-16 | 2008-04-16 | $7700.00 | Window Closed / Lapsed |