CMOS clock drivers with inductive coupling

Claim 2

A power conserving clock driver circuit comprising, a clock for producing a first clock signal and a second clock signal 180° out of phase with said first clock signal; a first driver circuit coupled to said first clock signal for producing at a first output a first power clock signal for driving a first capacitive load coupled thereto; a second driver circuit coupled to said second clock signal for producing at a second output a second power clock signal for driving a second capacitive load coupled thereto; means responsive to the change in level of said first clock signal to make said first driver circuit non-operative during a period of time; means responsive to the change in level of said second clock signal to make said second driver circuit non-operative during said period of time; and means to couple the capacitive load coupled to said first output to the capacitive load coupled to said second output, said means for coupling including an inductor and a switch operative during said period of time to transfer the charge on one said capacitive load through said inductor to the other said capacitive load.

Claim 3

The power conserving clock driver circuit of claim 1 wherein said time period is approximately the time for one half cycle of the natural resonant frequency of the circuit comprised of said inductor, said first capacitive load and said second capacitive load.

Claim 4

The power conserving clock driver circuit of claim 1 additionally including means to delay transmission of either said first and second clock pulse when the clock state transitions from a high to a low and to transmit undelayed said first and second clock pulse when the clock transitions from a low to a high.

Claim 5

The power conserving clock driver circuit of claim 1 additionally including means to delay transmission of either said first and second clock pulse when the clock state transitions from a low to a high and to transmit undelayed said first and second clock pulse when the clock transitions from a high to a low.

Claim 6

The power conserving clock driver circuit of claim 4 additionally including means to delay transmission of either said first and second clock pulse when the clock state transitions from a high to a low and to transmit undelayed said first and second clock pulse when the clock transitions from a low to a high.

Claim 7

A power conserving clock driver circuit comprising: a first terminal for coupling to a first power source; a second terminal for coupling to a second power source; a first and second P-type transistor coupled to said first terminal; a first and second N-type transistor coupled to said second terminal; said first P-type transistor and said first N-type transistor being coupled together at a first output terminal; said second P-type transistor and said second N-type transistor being coupled together at a second output terminal; an inductor with two leads, one lead of which is coupled to one said output terminal; and a third P-type transistor and a third N-type transistor connected in a pass gate configuration between said other lead of said inductor and said other output terminal.

Claim 8

A power conserving clock driver circuit comprising: a first terminal for coupling to a first power source; a second terminal for coupling to a second power source; a first and second P-type transistor coupled to said first terminal; a first and second N-type transistor coupled to said second terminal; said first P-type transistor and said first N-type transistor being coupled together at a first output terminal; said second P-type transistor and said second N-type transistor being coupled together at a second output terminal; an inductor with two leads, one lead of which is coupled to one said output terminal; and a third P-type transistor and a third N-type transistor connected in a pass gate configuration between said other lead of said inductor and said other output terminal.

Claim 9

The power conserving clock driver circuit of claim 6 additionally including: a differential clock for producing a first clock signal and a second clock signal 180° out of phase with said first clock signal; a first gate/delay circuit coupled to said first clock signal for producing a first gating signal which follows said first clock signal when said first clock signal transitions from high to low and delays for a time period T the tracking of said first clock signal when said first clock signal transitions from low to high; a second gate/delay circuit coupled to said first clock signal for producing a second gating signal which follows said first clock signal when said first clock signal transitions from low to high and delays for a time period T the tracking of said first clock signal when said first clock signal transitions from high to low; a third gate/delay circuit coupled to said second clock signal for producing a third gating signal which follows said second clock signal when said second clock signal transitions from high to low and delays for a time period T the tracking of said-third clock signal when said second clock signal transitions from low to high; a fourth gate/delay circuit coupled to said second clock signal for producing a fourth gating signal which follows said second clock signal when said second clock signal transitions from low to high and delays for a time period T the tracking of said second clock signal when said second clock signal transitions from high to low; means to couple said first, second, third and fourth clock signals respectively to the gates of said first N-type, first P-type, second N-type and second P-type transistors; a gate pulse producing circuit responsive to transitions of either said first or said second clock signal to produce a gate pulse of duration T; and means responsive to said gate pulse of duration T for turning on said third P-type and said third N-type transistors on.

Claim 10

The power conserving clock driver circuit of claim 7 wherein T is substantially one half cycle at the resonant frequency of the network formed by the capacitive load on each said output terminal and said inductor.