Semiconductor device including a pair of transistors having a common channel region, and method of making the same

Claim 2

A semiconductor device including: a) a first transistor which comprises: a gate electrode region formed in a surface of a semiconductor substrate and insulated from said substrate by an insulating film; a pair of diffused regions formed in the surface of said semiconductor substrate at its portions disposed at one side of said gate electrode region and spaced from each other by a predetermined distance; a substrate region formed in the surface of said semiconductor substrate and having three sides adjacent to said gate electrode region and said pair of diffused regions, respectively; and b) a second transistor formed in said semiconductor substrate so as to be symmetric with said first transistor with respect to a line along which said pair of diffused regions is aligned, said substrate region being common to said first and second transistors, wherein said first and second transistors comprise only one said pair of diffused regions which is common to said first and second transistors.

Claim 3

A semiconductor device including: a) a first transistor which comprises: a gate electrode region formed in a surface of a semiconductor substrate and insulated from said substrate by an insulating film; a pair of diffused regions formed in the surface of said semiconductor substrate at its portions disposed at one side of said gate electrode region and spaced from each other by a predetermined distance; a substrate region formed in the surface of said semiconductor substrate and having three sides adjacent to said gate electrode region and said pair of diffused regions, respectively; wherein said first gate electrode region and said pair of diffused regions are formed, respectively, in a first portion of said semiconductor substrate and a second portion thereof adjacent to said first portion, and, b) a second transistor having a second gate electrode region formed in a third portion spaced from said first portion with the second portion therebetween and wherein said second gate electrode region is adjacent to said pair of diffused regions with an insulating film interposed therebetween, said first and second transistors comprising only one said pair of diffused regions which is common to said first and second transistors.

Claim 4

A semiconductor device including: a) a first transistor which comprises: a gate electrode region formed in a surface of a semiconductor substrate and insulated from said substrate by an insulating film; a pair of diffused regions formed in the surface of said semiconductor substrate at its portions disposed at one side of said gate electrode region and spaced from each other by a predetermined distance; a substrate region formed in the surface of said semiconductor substrate and having three sides adjacent to said gate electrode region and said pair of diffused regions, respectively; wherein said first gate electrode region and said pair of diffused regions are formed, respectively, in a first portion of said semiconductor substrate and a second portion thereof adjacent to said first portion, and, b) a second transistor having a second gate electrode region formed in a third portion spaced from said first portion with the second portion therebetween and wherein said second gate electrode region is adjacent to said pair of diffused regions with an insulating film interposed therebetween, said first and second transistors comprising only one said pair of diffused regions which is common to said first and second transistors.

Claim 5

A semiconductor device comprising: a semiconductor substrate; a gate electrode formed in one surface of said semiconductor substrate and extending in a longitudinal direction along said one surface of said semiconductor substrate; an insulating film formed to insulate said gate electrode from said semiconductor substrate; and a source region, a channel region adjacent to said source regions, and a drain region adjacent to said channel region formed in said one surface of said semiconductor substrate in that order along said longitudinal direction and insulated from said gate electrode by said insulating film, wherein only one said source region and only one said drain region are common to a pair of transistors forming said semiconductor device.

Claim 6

A semiconductor device comprising: a semiconductor substrate; a gate electrode formed in one surface of said semiconductor substrate and extending in a longitudinal direction along said one surface of said semiconductor substrate; an insulating film formed to insulate said gate electrode from said semiconductor substrate; and a source region, a channel region adjacent to said source regions, and a drain region adjacent to said channel region formed in said one surface of said semiconductor substrate in that order along said longitudinal direction and insulated from said gate electrode by said insulating film, wherein only one said source region and only one said drain region are common to a pair of transistors forming said semiconductor device.

Claim 7

A semiconductor device according to claim 3, wherein said gate electrode is formed in a groove formed in said one surface of said semiconductor substrate, and wherein an inner wall and a bottom wall of said groove are covered by said insulating film.

Claim 8

A semiconductor device according to claim 3, wherein said gate electrode is formed of a conductive material embedded into a groove formed in said one surface of said semiconductor substrate.

Claim 9

A semiconductor device for performing an exclusive-OR logic operation, comprising: a pair of transistors which includes a) a semiconductor substrate; b) a pair of insulated gate electrodes located in said semiconductor substrate, wherein each transistor comprises one gate electrode of said pair of electrodes, said one gate electrode being spaced apart from the remaining gate electrode of said pair; c) a source region and a drain region located between gate electrodes of said pair and spaced apart from each other, wherein said pair of transistors comprises only one source region and only one drain region which are common to said pair of transistors; and d) a channel region being common to said pair of transistors and located between said source and drain regions for providing a conduction channel therebetween when a first voltage level applied to one gate electrode is different than a second voltage level applied to the remaining gate electrode of said pair.

Claim 10

A semiconductor device for performing an exclusive-OR logic operation, comprising: a pair of transistors which includes a) a semiconductor substrate; b) a pair of insulated gate electrodes located in said semiconductor substrate, wherein each transistor comprises one gate electrode of said pair of electrodes, said one gate electrode being spaced apart from the remaining gate electrode of said pair; c) a source region and a drain region located between gate electrodes of said pair and spaced apart from each other, wherein said pair of transistors comprises only one source region and only one drain region which are common to said pair of transistors; and d) a channel region being common to said pair of transistors and located between said source and drain regions for providing a conduction channel therebetween when a first voltage level applied to one gate electrode is different than a second voltage level applied to the remaining gate electrode of said pair.

Claim 11

A semiconductor device according to claim 6, wherein said semiconductor substrate is of a P-type and said source and drain regions are of an N-type.

Claim 12

A semiconductor device according to claim 6, wherein said pair of gate electrodes comprise an electrically conductive material located in a pair of substantially parallel grooves in said semiconducter substrate, each groove having inner side surfaces and a bottom surface covered with an insulating material disposed between said semiconductor substrate and said electrically conductive material.