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Method of manufacturing a semiconductor device in which a semiconductor zone is formed through diffusion from a strip of polycrystalline silicon

Assignee: US Philips Corp
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Filing: 1994-10-20
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Granted: 1996-04-16
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Expires: 2014-10-20
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Abstract

Abstract A method of manufacturing a semiconductor device whereby on a surface (3) of a semiconductor body (1) a conductor track (21) of polycrystalline silicon insulated from the surface (3) is provided in a layer of doped polycrystalline silicon (11) provided on a layer of insulating material (10), and whereby a strip of polycrystalline silicon (19, 35) is formed between an edge (18) of the conductor (21) and a portion (24, 34) of the surface (3) adjoining the edge (18), after which a semiconductor zone (30) is formed through diffusion of dopant from the conductor (21) through the strip (19, 35) into the semiconductor body (1). During the formation of the insulated conductor (21) and the strip of polycrystalline silicon (19, 35), a window (15) is etched into the layer of polycrystalline silicon (11) by means of a first etching mask (13), after which the insulating layer (10) is removed from the surface (3) within the window (15), the window (15) is provided at its edge (18) with a strip of polycrystalline silicon (19, 35), and the conductor (21) is etched into the layer of polycrystalline silicon (11) by means of a second etching mask (20), this second etching mask (20) covering at least a portion of the edge (18) of the window (15). Further conductors (22, 23) may be formed in the polycrystalline layer (11) next to the insulated conductor (21), all conductors (21, 22, 23) being given dimensions such as defined by the second etching mask (20).

Inventors

  • 👤 Willem Van Der Wel
  • 👤 Alexander C. L. Jansen
  • 👤 Ronald Koster

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 17:16
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; Y; Y10; Y10S; Y10S148/00; Y10S148/009

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 167 words
A method of manufacturing a semiconductor device whereby on a surface of a semiconductor body a conductor track of polycrystalline silicon insulated from the surface is formed in a layer of doped polycrystalline silicon provided on a layer of insulating material, and whereby a strip of polycrystalline silicon is formed between an edge of the conductor and a portion of the surface adjoining said edge, after which a semiconductor zone is formed in the semiconductor body through diffusion of dopant from the conductor through the strip, characterized in that a window is etched into the layer of polycrystalline silicon by means of a first etching mask after which the insulating layer is removed from the surface within said window, the window is provided at its edge with a strip of polycrystalline silicon, and the conductor track is formed in the layer of polycrystalline silicon by means of a second etching mask with said second etching mask covering at least a portion of the edge of the window.
Claim 2
Independent Claim 167 words
A method of manufacturing a semiconductor device whereby on a surface of a semiconductor body a conductor track of polycrystalline silicon insulated from the surface is formed in a layer of doped polycrystalline silicon provided on a layer of insulating material, and whereby a strip of polycrystalline silicon is formed between an edge of the conductor and a portion of the surface adjoining said edge, after which a semiconductor zone is formed in the semiconductor body through diffusion of dopant from the conductor through the strip, characterized in that a window is etched into the layer of polycrystalline silicon by means of a first etching mask after which the insulating layer is removed from the surface within said window, the window is provided at its edge with a strip of polycrystalline silicon, and the conductor track is formed in the layer of polycrystalline silicon by means of a second etching mask with said second etching mask covering at least a portion of the edge of the window.
Claim 3
Dependent Claim 57 words
A method as claimed in claim 1, characterized in that the layer of polycrystalline silicon is provided on an insulating layer formed on a surface of the semiconductor body to which field insulation regions adjoin, while the window is provided both above a field insulation region and above an active region bounded by said field insulation region.
Claim 4
Dependent Claim 58 words
A method as claimed in claim 2, characterized in that the window is provided at its edge with the strip of polycrystalline silicon through deposition of an auxiliary layer of polycrystalline silicon and by subjecting said auxiliary layer to a subsequent anisotropic etching treatment until the surface of the semiconductor body inside the window has been exposed again.
Claim 5
Dependent Claim 86 words
A method as claimed in claim 2, characterized in that the window is provided at its edge with the strip of polycrystalline silicon in that the layer of insulating material is etched away isotropically from the surface in a track situated below the edge of the window, in that then an auxiliary layer of polycrystaline silicon is deposited, and in that the auxiliary layer is subsequently subjected to an isotropic etching treatment until the surface of the semiconductor body inside the window has been exposed again.
Claim 6
Dependent Claim 58 words
A method as claimed in claim 1, characterized in that the window is provided at its edge with the strip of polycrystalline silicon through deposition of an auxiliary layer of polycrystalline silicon and by subjecting said auxiliary layer to a subsequent anisotropic etching treatment until the surface of the semiconductor body inside the window has been exposed again.
Claim 7
Dependent Claim 86 words
A method as claimed in claim 1, characterized in that the window is provided at its edge with the strip of polycrystalline silicon, in that the layer of insulating material is etched away isoptropically from the surface in a track situated below the edge of the window, in that then an auxiliary layer of polycrystalline silicon is deposited, and in that the auxiliary layer is subsequently subjected to an isotropic etching treatment until the surface of the semiconductor body inside the window has been exposed again.

References Cited (Backward Citations)

US4987089A Cited
EP0493853A1 Cited
US5244533A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-04-16 1999-10-16 2000-04-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-04-16 2003-10-16 2004-04-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-04-16 2007-10-16 2008-04-16 $7700.00 Window Closed / Lapsed

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