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Patent US5506627A successfully refreshed from Google Patents.
US5506627A
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Phase locked loop chain for locking audio sampling to serial digital component vide timing
Assignee: Grass Valley USA LLC
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Filing: 1994-06-10
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Granted: 1996-04-09
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Expires: 2014-06-10
Abstract
Abstract A phase locked loop (PLL) chain for locking audio sampling to serial digital component video timing has a deserializer that recovers a video sample clock signal from a serial digital video signal, the deserializer including a wide bandwidth PLL. A tracking filter in the form of a narrow bandwidth PLL having a low pass filter function reduces the jitter in the video sample clock signal to produce a stable reference clock signal. The stable reference clock signal is input to an audio sample clock generator to produce a stable audio sample clock signal for extracting audio data from the serial digital video signal.
Inventors
- 👤 John J. Ciardi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:08
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/60; H04N5/602; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/14; H04N21/00; H04N21/40; H04N21/43; H04N21/4302; H04N21/4305; H04N5/04; H04N5/12; H04N5/126
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
81 words
A phase locked loop chain comprising: a first wide bandwidth phase locked loop receiving a serial digital signal with an embedded clock component and recovering from the serial digital signal a first sample clock signal derived from the embedded clock component; a tracking filter having as an input the first sample clock signal to produce a stable reference clock signal; a second wide bandwidth phase locked loop for receiving the stable reference clock signal and generating a second sample clock signal.
Claim 2
Dependent Claim
81 words
A phase locked loop chain comprising: a first wide bandwidth phase locked loop receiving a serial digital signal with an embedded clock component and recovering from the serial digital signal a first sample clock signal derived from the embedded clock component; a tracking filter having as an input the first sample clock signal to produce a stable reference clock signal; a second wide bandwidth phase locked loop for receiving the stable reference clock signal and generating a second sample clock signal.
Claim 3
Dependent Claim
54 words
The phase locked loop chain as recited in claim 1 wherein the tracking filter comprises a crystal oscillator narrow bandwidth phase locked loop having parameters selected to provide a low pass filter response, the crystal oscillator narrow bandwidth phase locked loop receiving the first sample clock signal and producing the stable reference clock signal.
Claim 4
Dependent Claim
47 words
The phase locked loop chain as recited in claim 2 wherein the tracking filter further comprises means for maintaining the stable reference clock signal at the output of the crystal oscillator narrow bandwidth phase locked loop when the first sample clock signal is absent at the input.
Claim 5
Dependent Claim
89 words
The phase locked loop chain as recited in claim 2 wherein the crystal oscillator narrow bandwidth phase locked loop comprises: a phase detector having as a first input the first sample clock signal and as a second input the stable reference clock signal, and having as an output an error signal; a loop filter having as an input the error signal and as an output an error voltage; and a stable crystal oscillator having as an input the error voltage and as an output the stable reference clock signal.
Claim 6
Dependent Claim
113 words
The phase locked loop chain as recited in claim 4 wherein the crystal oscillator narrow bandwidth phase locked loop further comprises: a variable, precision voltage source to provide a reference voltage; and a multiplexer having as inputs the error voltage and the reference voltage and as an output a selected one of the two input voltages according to a select signal from the first wide bandwidth phase locked loop, the select signal indicating whether the serial digital signal is present at the input of the first wide bandwidth phase locked loop, and the selected one of the two input signals being input to the crystal oscillator to produce the stable reference clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-09 | 1999-10-09 | 2000-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-09 | 2003-10-09 | 2004-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-09 | 2007-10-09 | 2008-04-09 | $7700.00 | Window Closed / Lapsed |