Patent US4801160A successfully refreshed from Google Patents.
Patent US5506448A successfully refreshed from Google Patents.
US5506448A
Expired / Lapsed
US
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Semiconductor integrated circuit device having an improved packaging structure
Assignee: NEC Electronics Corp
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Filing: 1994-12-22
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Granted: 1996-04-09
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Expires: 2014-12-22
Abstract
Abstract Semiconductor IC device comprises an IC chip fixed to a top surface of a carrier board having top electrodes located on a periphery of the top surface. The carrier board further includes bottom electrodes on a bottom surface each connected to corresponding one of the top electrodes by an interconnection formed within the carrier board. The bottom electrodes of the carrier board are electrically connected to and mechanically fixed to internal electrodes of a package container having pin grids each connected to corresponding one of the internal electrodes. The bottom electrodes are arranged in a matrix for standardized structure. Variety of types of inexpensive carrier boards are prepared to variety of IC chips so that the number of the types of expensive package containers is reduced and a stock cost thereof is significantly reduced.
Inventors
- 👤 Sueo Morishige
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:32
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W70/67; H10W70/68; H10W70/682; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/547; H10W72/551; H10W72/552
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
190 words
A semiconductor integrated circuit comprising: at least one IC chip including therein a plurality of semiconductor elements and a plurality of bonding pads connected to said semiconductor elements; a carrier board having a top surface for mounting thereon a plurality of top electrodes, at least a part of said top electrodes being connected to a corresponding one of said bonding pads by a bonding wire, said carrier board further having a bottom surface for mounting thereon a plurality of bottom electrodes arranged in a matrix, and first interconnections formed within said carrier board and connecting each of said top electrodes with each corresponding one of said bottom electrodes, said IC chip being fixed to said top surface; and a package container having an internal surface for mounting a plurality of internal electrodes arranged in correspondence to said bottom electrodes, an external surface for mounting a plurality of external electrodes, and second interconnections connecting each of said internal electrodes to each corresponding one of said external electrodes, said carrier board being fixed to said package container through bonding each of said bottom electrodes to each corresponding one of said internal electrodes.
Claim 2
Dependent Claim
190 words
A semiconductor integrated circuit comprising: at least one IC chip including therein a plurality of semiconductor elements and a plurality of bonding pads connected to said semiconductor elements; a carrier board having a top surface for mounting thereon a plurality of top electrodes, at least a part of said top electrodes being connected to a corresponding one of said bonding pads by a bonding wire, said carrier board further having a bottom surface for mounting thereon a plurality of bottom electrodes arranged in a matrix, and first interconnections formed within said carrier board and connecting each of said top electrodes with each corresponding one of said bottom electrodes, said IC chip being fixed to said top surface; and a package container having an internal surface for mounting a plurality of internal electrodes arranged in correspondence to said bottom electrodes, an external surface for mounting a plurality of external electrodes, and second interconnections connecting each of said internal electrodes to each corresponding one of said external electrodes, said carrier board being fixed to said package container through bonding each of said bottom electrodes to each corresponding one of said internal electrodes.
Claim 3
Dependent Claim
24 words
A semiconductor integrated circuit as defined in claim 1 wherein said top electrodes are arranged in at least one row on said top surface.
Claim 4
Dependent Claim
17 words
A semiconductor integrated circuit as defined in claim 1 wherein said bonding wire is metallic capillary wire.
Claim 5
Dependent Claim
22 words
A semiconductor integrated circuit as defined in claim 1 wherein said carrier board includes a laminate of a plurality of resin layers.
Claim 6
Dependent Claim
22 words
A semiconductor integrated circuit as defined in claim 1 wherein said carrier board includes a laminate of a plurality of ceramic layers.
Claim 7
Dependent Claim
26 words
A semiconductor integrated circuit as defined in claim 1 further comprising a cap encapsulating said IC chip and said carrier board together with said package container.
Claim 8
Dependent Claim
26 words
A semiconductor integrated circuit as defined in claim 1 wherein each of said bottom electrodes is bonded to each corresponding internal electrode by a soldering material.
Claim 9
Dependent Claim
26 words
A semiconductor integrated circuit as defined in claim 1 wherein each of said bottom electrodes is bonded to each corresponding internal electrode by a conductive resin.
Claim 10
Dependent Claim
23 words
A semiconductor integrated circuit as defined in claim 1 wherein said IC chip is die-bonded to said top surface of said carrier board.
Claim 11
Dependent Claim
228 words
A semiconductor integrated circuit comprising: a plurality of IC chips each including a plurality of semiconductor elements and a plurality of bonding pads connected to said semiconductor elements; a plurality of carrier boards each positioned for mounting a corresponding one of said IC chips thereon, each of said carrier boards having a top surface for mounting a plurality of top electrodes and a corresponding one of said IC chips, at least a part of said top electrodes being connected to a corresponding one of said bonding pads by a bonding wire, each carrier board further having a bottom surface for mounting a plurality of bottom electrodes arranged in a matrix, and first interconnections formed within said carrier board and connecting each of said top electrodes with each corresponding one of said bottom electrodes; and a package container having a plurality of recesses each for receiving a corresponding one of said carrier boards, each of said recesses being provided with a plurality of internal electrodes arranged correspondingly to said bottom electrodes, said package container having an external surface for mounting thereon a plurality of external electrodes, and second interconnections connecting each of said internal electrodes to each corresponding one of said external electrodes, each of said carrier boards being fixed to said package container through bonding each of said bottom electrodes to each corresponding one of said internal electrodes.
Claim 12
Dependent Claim
228 words
A semiconductor integrated circuit comprising: a plurality of IC chips each including a plurality of semiconductor elements and a plurality of bonding pads connected to said semiconductor elements; a plurality of carrier boards each positioned for mounting a corresponding one of said IC chips thereon, each of said carrier boards having a top surface for mounting a plurality of top electrodes and a corresponding one of said IC chips, at least a part of said top electrodes being connected to a corresponding one of said bonding pads by a bonding wire, each carrier board further having a bottom surface for mounting a plurality of bottom electrodes arranged in a matrix, and first interconnections formed within said carrier board and connecting each of said top electrodes with each corresponding one of said bottom electrodes; and a package container having a plurality of recesses each for receiving a corresponding one of said carrier boards, each of said recesses being provided with a plurality of internal electrodes arranged correspondingly to said bottom electrodes, said package container having an external surface for mounting thereon a plurality of external electrodes, and second interconnections connecting each of said internal electrodes to each corresponding one of said external electrodes, each of said carrier boards being fixed to said package container through bonding each of said bottom electrodes to each corresponding one of said internal electrodes.
Claim 13
Dependent Claim
198 words
A semiconductor integrated circuit comprising: at least one IC chip including therein a plurality of semiconductor elements and a plurality of bonding pads connected to said semiconductor elements; a carrier board having a top surface for mounting thereon said IC chip and a plurality of top electrodes, at least a part of said top electrodes being connected to a corresponding one of said bonding pads by a bonding wire, said carrier board having a bottom surface for mounting thereon a plurality of bottom electrodes arranged in a matrix, and first interconnections formed within said carrier board and connecting each of said top electrodes with each corresponding one of said bottom electrodes; and a package container having a top surface having a plurality of external electrodes, a bottom surface implementing a radiator, an inner surface disposed opposite to said bottom surface and mounting a plurality of internal electrodes arranged correspondingly to said bottom electrodes, and second interconnections connecting each of said internal electrodes to each corresponding one of said external electrodes, said carrier board being fixed to said inner surface of said package container through bonding each of said bottom electrodes to each corresponding one of said internal electrodes.
Claim 14
Dependent Claim
198 words
A semiconductor integrated circuit comprising: at least one IC chip including therein a plurality of semiconductor elements and a plurality of bonding pads connected to said semiconductor elements; a carrier board having a top surface for mounting thereon said IC chip and a plurality of top electrodes, at least a part of said top electrodes being connected to a corresponding one of said bonding pads by a bonding wire, said carrier board having a bottom surface for mounting thereon a plurality of bottom electrodes arranged in a matrix, and first interconnections formed within said carrier board and connecting each of said top electrodes with each corresponding one of said bottom electrodes; and a package container having a top surface having a plurality of external electrodes, a bottom surface implementing a radiator, an inner surface disposed opposite to said bottom surface and mounting a plurality of internal electrodes arranged correspondingly to said bottom electrodes, and second interconnections connecting each of said internal electrodes to each corresponding one of said external electrodes, said carrier board being fixed to said inner surface of said package container through bonding each of said bottom electrodes to each corresponding one of said internal electrodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-09 | 1999-10-09 | 2000-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-09 | 2003-10-09 | 2004-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-09 | 2007-10-09 | 2008-04-09 | $7700.00 | Window Closed / Lapsed |