Power management system with adaptive control parameters for portable computer

Claim 3

The method of claim 1 further comprising the processor-implemented step of: establishing a fourth time interval and a fifth time interval; decreasing said first time interval by said fourth time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is not monitored prior to elapse of said fifth time interval.

Claim 4

The method of claim 2 wherein said step of decreasing said first time interval further comprises limiting said decreased, first time interval to a minimum interval.

Claim 5

The method of claim 1 wherein said step of increasing said first time interval further comprises limiting said increased, first time interval to a maximum interval.

Claim 8

The method of claim 5 further comprising the processor-implemented step of: establishing a fourth time interval and a fifth time interval; increasing said first time interval by said fourth time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is monitored prior to elapse of said fifth time interval.

Claim 9

The method of claim 6 wherein said step of increasing said first time interval further comprises limiting said increased, first time interval to a maximum interval.

Claim 10

The method of claim 5 wherein said step of decreasing said first time interval further comprises limiting said decreased, first time interval to a minimum interval.

Claim 17

Apparatus for controlling the power consumption of a personal computer system having interconnected on control and data bus lines a processor and at least one I/O device capable of operating in a reduced power consumption state, the apparatus comprising: logic implemented in said processor for establishing a first time interval, a second time interval, and a third time interval; logic implemented in said processor for monitoring signals on said lines for I/O activity associated with at least one said device; logic implemented in said processor for generating signals on said lines placing at least one said device in a reduced power consumption state upon elapse of said first time interval in which no I/O activity is monitored; and logic implemented in said processor for increasing said first time interval by said second time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is monitored on said lines prior to elapse of said third time interval.

Claim 18

Apparatus for controlling the power consumption of a personal computer system having interconnected on control and data bus lines a processor and at least one I/O device capable of operating in a reduced power consumption state, the apparatus comprising: logic implemented in said processor for establishing a first time interval, a second time interval, and a third time interval; logic implemented in said processor for monitoring signals on said lines for I/O activity associated with at least one said device; logic implemented in said processor for generating signals on said lines placing at least one said device in a reduced power consumption state upon elapse of said first time interval in which no I/O activity is monitored; and logic implemented in said processor for increasing said first time interval by said second time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is monitored on said lines prior to elapse of said third time interval.

Claim 19

The apparatus of claim 12 further comprising: logic implemented in said processor for establishing a fourth time interval and a fifth time interval; logic implemented in said processor for decreasing said first time interval by said fourth time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is not monitored on said lines until subsequent to elapse of said fifth time interval.

Claim 20

The apparatus of claim 13 wherein logic for decreasing said first time interval further comprises logic implemented in said processor for limiting said decreased, first time interval to a minimum interval.

Claim 21

The apparatus of claim 12 wherein said logic for increasing said first time interval further comprises logic implemented in said processor for limiting said increased, first time interval to a maximum interval.

Claim 22

The apparatus of claim 12 wherein said processor comprises a processor complex of said system.

Claim 23

The apparatus of claim 12 wherein said processor comprise a microcontroller separate from a processor complex of said system.

Claim 24

Apparatus for controlling the power consumption of a personal computer system having interconnected on control and data bus lines a processor and at least one I/O device capable of operating in a reduced power consumption state, the apparatus comprising: logic implemented in said processor for establishing a first time interval, a second time interval, and a third time interval; logic implemented in said processor for monitoring signals on said lines for I/O activity associated with at least one said device; logic implemented in said processor for generating signals on said lines placing at least one said device in a reduced power consumption state upon elapse of said first time interval in which no I/O activity is monitored; and logic implemented in said processor for decreasing said first time interval by said second time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is not monitored on said lines until subsequent to elapse of said third time interval.

Claim 25

Apparatus for controlling the power consumption of a personal computer system having interconnected on control and data bus lines a processor and at least one I/O device capable of operating in a reduced power consumption state, the apparatus comprising: logic implemented in said processor for establishing a first time interval, a second time interval, and a third time interval; logic implemented in said processor for monitoring signals on said lines for I/O activity associated with at least one said device; logic implemented in said processor for generating signals on said lines placing at least one said device in a reduced power consumption state upon elapse of said first time interval in which no I/O activity is monitored; and logic implemented in said processor for decreasing said first time interval by said second time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is not monitored on said lines until subsequent to elapse of said third time interval.

Claim 26

The apparatus of claim 18 further comprising: logic implemented in said processor for establishing a fourth time interval and a fifth time interval; logic implemented in said processor for increasing said first time interval by said fourth time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is monitored on said lines prior to elapse of said fifth time interval.

Claim 27

The apparatus of claim 19 wherein said logic for increasing said first time interval further comprises logic implemented in said processor for limiting said increased, first time interval to a maximum interval.

Claim 28

The apparatus of claim 18 wherein logic for decreasing said first time interval further comprises logic implemented in said processor for limiting said decreased, first time interval to a minimum interval.

Claim 29

The apparatus of claim 18 wherein said processor comprises a processor complex of said system.

Claim 30

The apparatus of claim 18 wherein said processor comprises a microcontroller separate from a processor complex of said system.

Claim 31

Apparatus for controlling the power consumption of a personal computer system having interconnected by control and data bus lines a processor and at least one I/O device capable of operating in a reduced power consumption state, the apparatus comprising: logic implemented in said processor for establishing a first time interval, a second time interval, a third time interval, a fourth time interval, and a fifth time interval; logic implemented in said processor for monitoring signals on said lines for I/O activity associated with at least one said device; logic implemented in said processor for generating signals on said lines placing at least one said device in a reduced power consumption state upon elapse of said first time interval in which no I/O activity is monitored; logic implemented in said processor for increasing said first time interval by said second time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is monitored on said lines prior to elapse of said third time interval; and logic implemented in said processor for decreasing said first time interval by said fourth time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is not monitored on said lines until subsequent to elapse of said fifth time interval.

Claim 32

Apparatus for controlling the power consumption of a personal computer system having interconnected by control and data bus lines a processor and at least one I/O device capable of operating in a reduced power consumption state, the apparatus comprising: logic implemented in said processor for establishing a first time interval, a second time interval, a third time interval, a fourth time interval, and a fifth time interval; logic implemented in said processor for monitoring signals on said lines for I/O activity associated with at least one said device; logic implemented in said processor for generating signals on said lines placing at least one said device in a reduced power consumption state upon elapse of said first time interval in which no I/O activity is monitored; logic implemented in said processor for increasing said first time interval by said second time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is monitored on said lines prior to elapse of said third time interval; and logic implemented in said processor for decreasing said first time interval by said fourth time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is not monitored on said lines until subsequent to elapse of said fifth time interval.

Claim 33

The apparatus of claim 24 wherein said processor comprises a processor complex of said system.

Claim 34

The apparatus of claim 24 wherein said processor comprises a microcontroller separate from a processor complex of said system.

Claim 35

A microcontroller connected to the system bus of a personal computer system for managing the power consumption of the system, the system including on said bus a processor complex and input/output (I/O) devices each capable of operating in a reduced power consumption state, the microcontroller comprising: at least one signal line connected to at least one said device for receiving signals indicative of I/O activity of said at least one device; at least one control line connected to said complex for granting and relinquishing said microcontroller control of said system bus as master; logic for establishing a first time interval, a second time interval, a third time interval, a fourth time interval, and a fifth time interval; logic for monitoring said at least one signal line for said signals indicative of said I/O activity; logic for issuing a bus request signal on said control line to said complex upon elapse of said first time interval in which no I/O activity is monitored for gaining control of said bus as master independent of said complex; logic for generating signals on said at least one signal line as master of said bus independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state; logic for deasserting on said at least one control line said bus request signal to said complex for releasing control of said bus as master upon completion of said signal generation placing said at least one device in a reduced power consumption state; logic for increasing said first time interval by said second time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is monitored on said at least one signal line prior to elapse of said third time interval; and logic for decreasing said first time interval by said fourth time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is not monitored on said at least one signal line until subsequent to elapse of said fifth time interval.

Claim 36

A microcontroller connected to the system bus of a personal computer system for managing the power consumption of the system, the system including on said bus a processor complex and input/output (I/O) devices each capable of operating in a reduced power consumption state, the microcontroller comprising: at least one signal line connected to at least one said device for receiving signals indicative of I/O activity of said at least one device; at least one control line connected to said complex for granting and relinquishing said microcontroller control of said system bus as master; logic for establishing a first time interval, a second time interval, a third time interval, a fourth time interval, and a fifth time interval; logic for monitoring said at least one signal line for said signals indicative of said I/O activity; logic for issuing a bus request signal on said control line to said complex upon elapse of said first time interval in which no I/O activity is monitored for gaining control of said bus as master independent of said complex; logic for generating signals on said at least one signal line as master of said bus independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state; logic for deasserting on said at least one control line said bus request signal to said complex for releasing control of said bus as master upon completion of said signal generation placing said at least one device in a reduced power consumption state; logic for increasing said first time interval by said second time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is monitored on said at least one signal line prior to elapse of said third time interval; and logic for decreasing said first time interval by said fourth time interval if, subsequent to placement of said device in a reduced power consumption state, I/O activity of at least one said device is not monitored on said at least one signal line until subsequent to elapse of said fifth time interval.

Claim 37

The microcontroller of claim 27 wherein said processor complex includes a central processing unit (CPU), said microcontroller further comprising: a CPU clock controller connected to said system bus; and logic for generating signals on said system bus as master independent of said complex to said CPU clock controller for reducing the processing speed of said CPU.

Claim 38

The microcontroller of claim 28 wherein said CPU processing speed is reduced to 0 megahertz.

Claim 39

The microcontroller of claim 28 wherein said CPU processing speed is reduced to 3.125 megahertz.

Claim 40

The microcontroller of claim 27 wherein said first time interval is a default interval.

Claim 41

The microcontroller of claim 27 wherein said establishing said first time interval comprises establishing by a user a time interval for each said at least one device.