Nonvolatile memory with a programmable output of selectable width and a method for controlling the nonvolatile memory to switch between different output widths

Claim 2

A nonvolatile memory, comprising: (A) a memory array; (B) a plurality of data pads; (C) data width control circuitry coupled to (1) the plurality of data pads and (2) the memory array, the data width control circuitry selectively coupling the plurality of data pads to the memory array; (D) a data width configuration cell having a nonvolatile memory cell; (E) data width select circuitry coupled to (1) the data width configuration cell and (2) the data width control circuitry, wherein when the data width configuration cell is in a first state, the data width select circuitry controls the data width control circuitry to couple the memory array to a first portion of the plurality of data pads such that the nonvolatile memory has a first data width, wherein when the data width configuration cell is in a second state, the data width select circuitry controls the data width control circuitry to couple the memory array to a second portion of the plurality of data pads such that the nonvolatile memory has a second data width.

Claim 3

The nonvolatile memory of claim 1, wherein the first portion of the plurality of data pads is word wide and the second portion of the plurality of data pads is byte wide.

Claim 4

The nonvolatile memory of claim 1, wherein the first portion of the plurality of data pads includes all of the plurality of data pads and the second portion of the plurality of data pads includes half of the plurality of data pads.

Claim 5

The nonvolatile memory of claim 1, wherein the first state of the data width configuration cell is a programmed state and the second state is an erased state.

Claim 6

The nonvolatile memory of claim 1, wherein the memory array includes a plurality of electrically erasable and electrically programmable nonvolatile memory cells.

Claim 7

The nonvolatile memory of claim 1, wherein the memory array includes a first sub-array and a second sub-array, wherein when the data width control circuitry couples the memory array to the second portion of the plurality of data pads, the data width select circuitry receives an address bit signal from one of the plurality of data pads not within the second portion of the plurality of data pads to control the data width control circuitry to selectively couple one of the first and second sub-arrays of the memory array to the second portion of the plurality of data pads.

Claim 8

The nonvolatile memory of claim 6, wherein the data width control circuitry further includes output multiplexing circuitry and input multiplexing circuitry, wherein the data width select circuitry controls the output multiplexing circuitry to selectively couple one of the first and second sub-arrays to the second portion of the plurality of data pads during reading of the nonvolatile memory, wherein the data width select circuitry controls the input multiplexing circuitry to selectively couple the second portion of the plurality of data pads to one of the first and second sub-arrays during programming of the nonvolatile memory.

Claim 9

The nonvolatile memory of claim 1, further comprising a data width control pad coupled to the data width select circuitry for providing a data width control signal to the data width select circuitry when the data width configuration cell is in the first state, wherein when the data width control signal is in a first voltage state, the data width select circuitry causes the data width control circuitry to couple the memory array to the first portion of the plurality of data pads, wherein when the data width control signal is in a second voltage state, the data width select circuitry causes the data width control circuitry to couple the memory array to the second portion of the plurality of data pads.

Claim 10

The nonvolatile memory of claim 8, wherein the memory array includes a first sub-array and a second sub-array, wherein when the data width control signal is in the second voltage state, the data width select circuitry receives an address bit signal from one of the plurality of data pads not within the second portion of the plurality of data pads to control the data width control circuitry to selectively couple one of the first and second sub-arrays of the memory array to the second portion of the plurality of data pads.

Claim 11

A nonvolatile memory, comprising: (a) a first memory array; (b) a second memory array; (c) a first plurality of data pads; (d) a second plurality of data pads; (e) data width control circuitry coupled to (1) the first and second plurality of data pads and (2) the first and second memory arrays, the data width control circuitry selectively coupling the first and second plurality of data pad to the first and second memory arrays; (f) a data width configuration cell having a nonvolatile memory cell; (g) data width select circuitry coupled to (1) the data width configuration cell and (2) the data width control circuitry, wherein when the data width configuration cell is in a first state, the data width select circuitry controls the data width control circuitry to couple the first and second memory arrays to the first and second plurality of data pads such that the nonvolatile memory has a first data width, wherein when the data width configuration cell is in a second state, the data width select circuitry controls the data width control circuitry to couple the first and second memory arrays to the first plurality of data pads such that the nonvolatile memory has a second data width.

Claim 12

A nonvolatile memory, comprising: (a) a first memory array; (b) a second memory array; (c) a first plurality of data pads; (d) a second plurality of data pads; (e) data width control circuitry coupled to (1) the first and second plurality of data pads and (2) the first and second memory arrays, the data width control circuitry selectively coupling the first and second plurality of data pad to the first and second memory arrays; (f) a data width configuration cell having a nonvolatile memory cell; (g) data width select circuitry coupled to (1) the data width configuration cell and (2) the data width control circuitry, wherein when the data width configuration cell is in a first state, the data width select circuitry controls the data width control circuitry to couple the first and second memory arrays to the first and second plurality of data pads such that the nonvolatile memory has a first data width, wherein when the data width configuration cell is in a second state, the data width select circuitry controls the data width control circuitry to couple the first and second memory arrays to the first plurality of data pads such that the nonvolatile memory has a second data width.

Claim 13

The nonvolatile memory of claim 10, further comprising a data width control pad coupled to the data width select circuitry for providing a data width control signal to the data width select circuitry when the data width configuration cell is in the first state, wherein when the data width control signal is in a first voltage state, the data width select circuitry causes the data width control circuitry to couple the first and second memory arrays to the first and second plurality of data pads, wherein when the data width control signal is in a second voltage state, the data width select circuitry causes the data width control circuitry to couple the first and second memory arrays to the first plurality of data pads.

Claim 14

The nonvolatile memory of claim 11, wherein when the data width control circuitry couples the first and second memory arrays to the first plurality of data pads, the data width select circuitry receives an address bit signal from one of the second plurality of data pads to control the data width control circuitry to selectively couple one of the first and second memory arrays to the first plurality of data pads.

Claim 15

The nonvolatile memory of claim 12, wherein the data width control circuitry further includes output multiplexing circuitry and input multiplexing circuitry, wherein the data width select circuitry controls the output multiplexing circuitry to selectively couple one of the first and second memory arrays to the first plurality of data pads during reading of the nonvolatile memory when the first and second memory arrays are to be coupled to the first plurality of data pads, wherein the data width select circuitry controls the input multiplexing circuitry to selectively couple the first plurality of data pads to one of the first and second memory arrays during programming of the nonvolatile memory when the first and second memory arrays are to be coupled to the first plurality of data pads.

Claim 16

The nonvolatile memory of claim 10, wherein the first data width is word wide and the second data width is byte wide.

Claim 17

The nonvolatile memory of claim 10, wherein the first state of the data width configuration cell is a programmed state and the second state is an erased state.

Claim 18

The nonvolatile memory of claim 10, wherein the memory array includes a plurality of electrically erasable and electrically programmable nonvolatile memory cells.

Claim 19

A computer system, comprising: (A) a system bus; (B) a central processing unit (CPU) coupled to the system bus; (C) a plurality of peripheral devices, each of which being coupled to the system bus; (D) a nonvolatile memory coupled to the system bus, wherein the nonvolatile memory further comprises (i) a first memory array; (ii) a second memory array; (iii) a first plurality of data pads; (iv) a second plurality of data pads; (v) data width control circuitry coupled to (1) the first and second plurality of data pads and (2) the first and second memory arrays, the data width control circuitry selectively coupling the first and second plurality of data pads to the first and second memory arrays; (vi) a data width configuration cell having a nonvolatile memory cell; (vii) data width select circuitry coupled to (1) the data width configuration cell and (2) the data width control circuitry, wherein when the data width configuration cell is in a first state, the data width select circuitry controls the data width control circuitry to couple the first and second memory arrays to the first and second plurality of data pads such that the nonvolatile memory has a first data width, wherein when the data width configuration cell is in a second state, the data width select circuitry controls the data width control circuitry to couple the first and second memory arrays to the first plurality of data pads such that the nonvolatile memory has a second data width.

Claim 20

A computer system, comprising: (A) a system bus; (B) a central processing unit (CPU) coupled to the system bus; (C) a plurality of peripheral devices, each of which being coupled to the system bus; (D) a nonvolatile memory coupled to the system bus, wherein the nonvolatile memory further comprises (i) a first memory array; (ii) a second memory array; (iii) a first plurality of data pads; (iv) a second plurality of data pads; (v) data width control circuitry coupled to (1) the first and second plurality of data pads and (2) the first and second memory arrays, the data width control circuitry selectively coupling the first and second plurality of data pads to the first and second memory arrays; (vi) a data width configuration cell having a nonvolatile memory cell; (vii) data width select circuitry coupled to (1) the data width configuration cell and (2) the data width control circuitry, wherein when the data width configuration cell is in a first state, the data width select circuitry controls the data width control circuitry to couple the first and second memory arrays to the first and second plurality of data pads such that the nonvolatile memory has a first data width, wherein when the data width configuration cell is in a second state, the data width select circuitry controls the data width control circuitry to couple the first and second memory arrays to the first plurality of data pads such that the nonvolatile memory has a second data width.

Claim 21

The computer system of claim 17, further comprising a data width control pad coupled to the data width select circuitry for providing a data width control signal to the data width select circuitry when the data width configuration cell is in the first state, wherein when the data width control signal is in a first voltage state, the data width select circuitry causes the data width control circuitry to couple the first and second memory arrays to the first and second plurality of data pads, wherein when the data width control signal is in a second voltage state, the data width select circuitry causes the data width control circuitry to couple the first and second memory arrays to the first plurality of data pads.

Claim 22

The computer system of claim 18, wherein when the data width control circuitry couples the first and second memory arrays to the first plurality of data pads, the data width select circuitry receives an address bit signal from one of the second plurality of data pads to control the data width control circuitry to selectively couple one of the first and second memory arrays to the first plurality of data pads.

Claim 23

The computer system of claim 19, wherein the data width control circuitry further includes output multiplexing circuitry and input multiplexing circuitry, wherein the data width select circuitry controls the output multiplexing circuitry to selectively couple one of the first and second memory arrays to the first plurality of data pads during reading of the nonvolatile memory when the first and second memory arrays are to be coupled to the first plurality of data pads, wherein the data width select circuitry controls the input multiplexing circuitry to selectively couple the first plurality of data pads to one of the first and second memory arrays during programming of the nonvolatile memory when the first and second memory arrays are to be coupled to the first plurality of data pads.

Claim 24

The computer system of claim 20, wherein the first data width is word wide and the second data width is byte wide.

Claim 25

The computer system of claim 21, wherein the first state of the data width configuration cell is a programmed state and the second state is an erased state.

Claim 26

The computer system of claim 22, wherein the memory array includes a plurality of electrically erasable and electrically programmable nonvolatile memory cells.

Claim 29

The method of claim 24, wherein the first data width is word wide and the second data width is byte wide.

Claim 30

The method of claim 24, wherein the step (C) further comprises the steps of: (a) receiving a control signal in the data width select mean, wherein the control signal can be in a first voltage state and a second voltage state; (b) if the control signal is in the first voltage state, then coupling the first memory array to the first plurality of data pads and the second memory array to the second plurality of data pads; (c) if the control signal is in the second voltage state, then (I) receiving an address input signal from one of the second plurality of data pads by the data width select circuitry; and (II) selectively coupling one of the first and second memory arrays to the first plurality of data pads depending on the address input signal.

Claim 31

The method of claim 26, wherein the first state of the data width configuration cell is a programmed state and the second state is an erased state, wherein the first voltage state of the control signal is logical high state and the second voltage state is logical low state.