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US5504749A
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Apparatus for reading out address information
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-11-03
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Granted: 1996-04-02
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Expires: 2014-11-03
Abstract
Abstract An address information reading-out apparatus of an FDDI network system for transmitting a packet composed of a plurality of m-bit symbols includes an m-bit data bus, an n×m-bit data bus, a control signal generator for detecting start and control symbols among the plurality of symbols received via said m-bit data bus and generating control signals, an input latch for alternately latching the address symbols having an odd number and the address symbols having an even number among the plurality of symbols, in response to the control signal of the control signal generator, an output latch for latching a pair of address symbols from the input latch in response to the control signal of the control signal generator and outputting onto the n×m-bit data bus, and a content addressable memory for receiving the address symbol from the n×m-bit data bus in response to the control signal of the control signal generator, determining whether the input symbol matches predetermined address information, and if so, generating a reading-out signal. Therefore, address information can be read out by hardware, thereby reducing the load on the CPU of the system and improving the performance of the system.
Inventors
- 👤 Young-chang Cheon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:43
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/40052; H04L12/40071; H04L9/00; H04L9/40; H04L12/40169
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
173 words
An apparatus for reading out address information of an FDDI network system for transmitting a packet having a plurality of m-bit symbols, comprising: an m-bit data bus; an n×m-bit data bus; control signal generating means for detecting a start symbol and a control symbol among said plurality of m-bit symbols received via said m-bit data bus, and generating control signals; input latch means for alternately latching odd-numbered and even-numbered address symbols among said plurality of m-bit symbols in response to the control signal of said control signals generating means; output latch means for latching a pair of address symbols from said input latch means in response to the control signals of said control signal generating means, and outputting said latched pair of address symbols onto said n×m-bit data bus; content addressable memory means for receiving said pair of address symbols from said n×m-bit data bus in response to the control signals of said control signal generating means, determining whether the input symbols match predetermined address information and, if so, generating a reading-out signal.
Claim 2
Independent Claim
173 words
An apparatus for reading out address information of an FDDI network system for transmitting a packet having a plurality of m-bit symbols, comprising: an m-bit data bus; an n×m-bit data bus; control signal generating means for detecting a start symbol and a control symbol among said plurality of m-bit symbols received via said m-bit data bus, and generating control signals; input latch means for alternately latching odd-numbered and even-numbered address symbols among said plurality of m-bit symbols in response to the control signal of said control signals generating means; output latch means for latching a pair of address symbols from said input latch means in response to the control signals of said control signal generating means, and outputting said latched pair of address symbols onto said n×m-bit data bus; content addressable memory means for receiving said pair of address symbols from said n×m-bit data bus in response to the control signals of said control signal generating means, determining whether the input symbols match predetermined address information and, if so, generating a reading-out signal.
Claim 3
Dependent Claim
140 words
An apparatus for reading out address information as claimed in claim 1, wherein said control signal generating means comprises: a first detector for generating a first detection signal by detecting the start symbol of said start and control symbols; a second detector for generating a second detection signal by detecting the control symbol of said start and control symbols; state machine means for generating an odd number latch control signal, an even number latch control signal, an output latch enable control signal and state control signals, which are synchronized with a first clock signal in response to said first and second detection signals; and memory control machine means for generating an enable control signal and a write control signal of said content addressable memory means, which are synchronized with a second clock signal in response to said state control signals.
Claim 4
Dependent Claim
68 words
An apparatus for reading out address information as claimed in claim 2, wherein said input latch means comprises: first latch means connected to said m-bit data bus, for latching an odd number address symbol in response to said odd number latch control signal; and second latch means connected said m-bit data bus, for latching an even number address symbol in response to said even number latch control signal.
Claim 5
Dependent Claim
91 words
An apparatus for reading out address information as claimed in claim 3, wherein said output latch means comprises: third latch means connected to said first latch means and enabled by said output latch enable control signal, for latching the output of said first latch means in response to said odd number latch control signal; and fourth latch means connected to said second latch means and enabled by said output latch enable control signal, for latching the output of said second latch means in response to said even number latch control signal.
Claim 6
Independent Claim
182 words
An apparatus for use in reading out address information of an FDDI network system comprising: a first data bus for transmitting a plurality of sequential symbols of a packet including a start symbol, and a plurality of alternating odd-numbered and even-numbered destination address symbols; a first detector coupled to the first data bus for detecting the start symbol and outputting a first detection signal responsive to detecting the start symbol; first and second latches coupled to the first data bus for sequentially latching a plurality of pairs of destination addresses responsive to the first detection signal, each pair of destination addresses including one of the odd-numbered destination address symbols and one of the even-numbered destination address symbols; a second data bus coupled to both the first and second latches for simultaneously transmitting one of the pairs of destination addresses; and a content addressable memory having an input coupled to the second data bus for receiving the pairs of destination addresses and for generating a reading-out signal responsive to the plurality of alternating odd-numbered and even-numbered destination address symbols matching stored address information.
Claim 7
Independent Claim
182 words
An apparatus for use in reading out address information of an FDDI network system comprising: a first data bus for transmitting a plurality of sequential symbols of a packet including a start symbol, and a plurality of alternating odd-numbered and even-numbered destination address symbols; a first detector coupled to the first data bus for detecting the start symbol and outputting a first detection signal responsive to detecting the start symbol; first and second latches coupled to the first data bus for sequentially latching a plurality of pairs of destination addresses responsive to the first detection signal, each pair of destination addresses including one of the odd-numbered destination address symbols and one of the even-numbered destination address symbols; a second data bus coupled to both the first and second latches for simultaneously transmitting one of the pairs of destination addresses; and a content addressable memory having an input coupled to the second data bus for receiving the pairs of destination addresses and for generating a reading-out signal responsive to the plurality of alternating odd-numbered and even-numbered destination address symbols matching stored address information.
References Cited (Backward Citations)
US5235593A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |