Single-chip GPS receiver digital signal processing and microcomputer

Claim 2

A digital integrated circuit (IC) for providing digital processing in a global positioning system (GPS) navigation environment, the IC comprising: a single semiconductor substrate providing for connection to a single power supply voltage; a microcomputer (CPU) having address and data bus connections to a random access memory (RAM) and a boot-up read only memory (ROM), said microcomputer, said RAM, said ROM, and all of said bus connections being integrated on said substrate and providing acquisition and tracking of navigation satellite transmissions; a multi-channel GPS receiver including a digital signal processing unit connected to support said acquisition and tracking by the microcomputer and providing satellite navigation including code correlation, position and velocity calculation, said multi-channel GPS receiver being integrated on said substrate; and a peripheral interface providing connection of an analog-to-digital converter (ADC) and a dual universal asynchronous receiver/transmitter (DUART) to the CPU, said peripheral interface, said ADC, and said DUART being integrated on said substrate.

Claim 3

An integrated circuit (IC) with a digital signal processor (DSP) for determining a position and velocity of a satellite navigation receiver from radio signals transmitted by orbiting navigation satellites, the DSP comprising: a single semiconductor chip having a plurality of input/output (I/O) pins for external connections; a set of IC pin multiplexers fully disposed on the chip and connected to said I/O pins; a dual universal asynchronous receiver transmitter (DUART) connected to the set of IC pin multiplexers for serial data communications and fully disposed on the chip; a read only memory (ROM) comprising a boot code program for selecting an external memory having a custom initialization code and fully disposed on the chip; a random access memory (RAM) mapped in a memory space adjacent to the ROM and fully disposed on the chip; a microcomputer (CPU) connected to the ROM and the RAM and providing support for GPS navigation digital processing, GPS code correlation and position and velocity calculation, user keyboard and display interfacing, and general input/output functions, and fully disposed on the chip; a plurality of GPS receiver channels connected to the set of IC pin multiplexers and the CPU for demodulating navigation satellite carrier signals simultaneously received from a plurality of orbiting GPS satellites, and fully disposed on the chip; and a global channel controller connected to the set of IC pin multiplexers and having a sample circuit connected for intermediate frequency (IF) demodulation, a process interrupt circuit connected to the CPU, a millisecond event counter connected to the CPU, an interrupt generator connected to the CPU, a real time clock (RTC) connected to the CPU, an IF input selector connected to the set of IC pin multiplexers, and a channel controller connected to the plurality of GPS receiver channels, and fully disposed on the chip.

Claim 4

An integrated circuit (IC) with a digital signal processor (DSP) for determining a position and velocity of a satellite navigation receiver from radio signals transmitted by orbiting navigation satellites, the DSP comprising: a single semiconductor chip having a plurality of input/output (I/O) pins for external connections; a set of IC pin multiplexers fully disposed on the chip and connected to said I/O pins; a dual universal asynchronous receiver transmitter (DUART) connected to the set of IC pin multiplexers for serial data communications and fully disposed on the chip; a read only memory (ROM) comprising a boot code program for selecting an external memory having a custom initialization code and fully disposed on the chip; a random access memory (RAM) mapped in a memory space adjacent to the ROM and fully disposed on the chip; a microcomputer (CPU) connected to the ROM and the RAM and providing support for GPS navigation digital processing, GPS code correlation and position and velocity calculation, user keyboard and display interfacing, and general input/output functions, and fully disposed on the chip; a plurality of GPS receiver channels connected to the set of IC pin multiplexers and the CPU for demodulating navigation satellite carrier signals simultaneously received from a plurality of orbiting GPS satellites, and fully disposed on the chip; and a global channel controller connected to the set of IC pin multiplexers and having a sample circuit connected for intermediate frequency (IF) demodulation, a process interrupt circuit connected to the CPU, a millisecond event counter connected to the CPU, an interrupt generator connected to the CPU, a real time clock (RTC) connected to the CPU, an IF input selector connected to the set of IC pin multiplexers, and a channel controller connected to the plurality of GPS receiver channels, and fully disposed on the chip.

Claim 5

The IC of claim 2, wherein the microcomputer comprises a thirty-two bit processor and includes master/slave means for disabling the microcomputer means providing operation of the IC as a peripheral during software development with an emulator.

Claim 6

The IC of claim 3, wherein: the CPU includes thirty-two address lines of which a portion are connected directly to an external interface of the IC and another portion are brought to a shared external interface of the IC wherein the number of interface pins required for the IC is conserved.

Claim 7

The IC of claim 2, wherein the DUART comprises a communications controller providing request-to-send and clear-to-send communication-interface controls and a crystal oscillator interface for an external crystal input wherein said crystal oscillator provides a basic clock for communication rates of the DUART.

Claim 8

The IC of claim 2, wherein the plurality of GPS receiver channels includes eight channels for providing searching and tracking GPS satellites and their respective Doppler influenced carrier signals, and code multiple access code phases.

Claim 9

The IC of claim 2, wherein the plurality of GPS receiver channels includes a set of intermediate frequency (IF) inputs for a two-bit quadrature input.

Claim 10

The IC of claim 7, wherein the plurality of GPS receiver channels further includes multiplexer means for accepting a plurality of types of IF signal inputs.

Claim 11

The IC of claim 7, wherein the plurality of GPS receiver channels further includes mode-changing means for accepting a plurality of types of IF signal inputs, and wherein: in a normal mode, said IF inputs are directly available; in a sampler mode, said IF inputs are directed to a sampler circuit; in a gyro mode, a pair of single-bit inputs are steered to said sampler circuit and a pair of additional inputs connect to a pair of gyro sampler flip-flops; and in a signed/magnitude input mode, a sign input and two magnitude inputs to said sampler are accepted, together with a sampler clock.

Claim 12

The IC of claim 2, wherein: the chip is substantially square and has: disposed generally in a first quadrant a system integration module (SIM) and pin multiplexer interface for connection of the IC to external devices; disposed generally in a second quadrant the CPU coupled to said SIM and pin multiplexer interface; disposed generally in a third quadrant said GPS receiver coupled to the CPU; and disposed generally in a fourth quadrant the peripheral means and said RAM and ROM coupled to the CPU .

Claim 13

The IC of claim 2, further comprising: power-saving means connected to the plurality of GPS receiver channels and for turning-off the clock signal to a variable number of said channels.