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US5504454A
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Demodulator for powerline carrier communications
Assignee: Northrop Grumman Systems Corp
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Filing: 1995-01-30
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Granted: 1996-04-02
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Expires: 2015-01-30
Abstract
Abstract A method for demodulating the carrier signal of powerline communication networks. The method involves demodulating an HDLC data body that had been modulated through differential phase shift keyed modulation. Under the method, the data body is split with data input into a single bit digital delay circuit which outputs a delayed or "previous" binary data bit. A "present" binary data bit is input to one input of an XNOR circuit and the previous binary data bit is input into a second input of the XNOR circuit. When the present binary data bit and the previous binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value. When the present binary data bit and the previous binary data bit have like phases, the XNOR circuit outputs a second binary data bit value. Preferably, the demodulated data is input into a post detection filter. The demodulation method also preferably involves the step of processing the demodulated data through a receive data correlator, a data body state machine and a variable divide counter.
Inventors
- 👤 Kenneth E. Daggett
- 👤 Dirk J. Boomgaard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:02
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/233; H04L27/2331; H02; H02J; H02J13/00; H02J13/13; H02J13/1311; H02J13/1313; H04B; H04B3/00; H04B3/54; H04B3/542; H04B2203/00; H04B2203/54; H04B2203/5404; H04B2203/5408; H04B2203/5416; H04B2203/5429; H04B2203/5445; H04B2203/5462; H04B2203/5483; H04B2203/5491; Y; Y02; Y02E; Y02E60/00; Y04; Y04S; Y04S40/00; Y04S40/12; Y04S40/121
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
171 words
A method of demodulating an HDLC data body which had been modulated through differential phase shift keyed modulation, the method comprises the steps of: sampling the data body in a sampling flip-flop which splits the data body into first and second identical portions; inputting the first portion of the data body into a single bit digital delay circuit which outputs a previous binary data bit; inputting the second portion of the previous binary data bit into a first input of an XNOR circuit; inputting the data body directly into a secure input of the XNOR circuit so that of the data body, a present data bit and a previous data bit are compared by the XNOR circuit and when the previous binary data bit and the next consecutive binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value, and when the previous binary data bit and the next consecutive binary data bit have like phases, the XNOR circuit outputs a second binary data bit value.
Claim 2
Independent Claim
171 words
A method of demodulating an HDLC data body which had been modulated through differential phase shift keyed modulation, the method comprises the steps of: sampling the data body in a sampling flip-flop which splits the data body into first and second identical portions; inputting the first portion of the data body into a single bit digital delay circuit which outputs a previous binary data bit; inputting the second portion of the previous binary data bit into a first input of an XNOR circuit; inputting the data body directly into a secure input of the XNOR circuit so that of the data body, a present data bit and a previous data bit are compared by the XNOR circuit and when the previous binary data bit and the next consecutive binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value, and when the previous binary data bit and the next consecutive binary data bit have like phases, the XNOR circuit outputs a second binary data bit value.
Claim 3
Dependent Claim
19 words
The method of claim 1 further comprising the step of inputting the demodulated data into a post detection filter.
Claim 4
Dependent Claim
16 words
The method of claim 2 wherein the post detection filter comprises a two stage RC filter.
Claim 5
Dependent Claim
20 words
The method of claim 3 wherein the filter has a time constant for each stage of approximately one-quarter bit time.
Claim 6
Dependent Claim
29 words
The method of claim 2 further comprising the step of processing the demodulated data through a receive data correlator, a data body state machine and a variable divide counter.
Claim 7
Dependent Claim
35 words
The method of claim 5 wherein the sampling flip-flop, the delay circuit, the XNOR circuit, the port detection filter, the correlator, the state machine and the adaptor are incorporated within a field programmable gate array.
Claim 8
Dependent Claim
21 words
The method of claim 1 wherein the single bit delay is comprised of a shift register having at least thirty-two elements.
Claim 9
Dependent Claim
19 words
The method of claim 7 wherein the single bit delay is comprised of a shift register having forty elements.
Claim 10
Dependent Claim
24 words
The method of claim 1 wherein the sampling flip-flop, the delay circuit and the XNOR gate are provided within a field programmable gate array.
Claim 11
Dependent Claim
18 words
The apparatus of claim 1 wherein the delay circuit comprises a shift register having at least thirty-two elements.
Claim 12
Dependent Claim
24 words
The apparatus of claim 1 wherein the sampling flip-flop, the delay circuit and the XNOR circuit are incorporated within a field programmable gate array.
Claim 13
Independent Claim
153 words
An apparatus for demodulating an HDLC data body which had been modulated by Differential Phase Shift Keyed modulation comprising: a sampling flip-flop which splits the data body into first and second identical portions; a single bit digital delay circuit that receives a binary data bit from the first data body portion and outputs a delayed binary data bit; an XNOR circuit having first and second inputs in which a present binary data bit from the second data portion is input into the first XNOR circuit input and the delayed binary bit is input into the second XNOR circuit input, and wherein the XNOR circuit outputs a first binary data bit value when the present binary data bit and the delayed binary data bit have unlike phases, and wherein the XNOR circuit outputs a second binary data bit value when the present binary data bit and the delayed binary data bit have like phases.
Claim 14
Independent Claim
153 words
An apparatus for demodulating an HDLC data body which had been modulated by Differential Phase Shift Keyed modulation comprising: a sampling flip-flop which splits the data body into first and second identical portions; a single bit digital delay circuit that receives a binary data bit from the first data body portion and outputs a delayed binary data bit; an XNOR circuit having first and second inputs in which a present binary data bit from the second data portion is input into the first XNOR circuit input and the delayed binary bit is input into the second XNOR circuit input, and wherein the XNOR circuit outputs a first binary data bit value when the present binary data bit and the delayed binary data bit have unlike phases, and wherein the XNOR circuit outputs a second binary data bit value when the present binary data bit and the delayed binary data bit have like phases.
Claim 15
Dependent Claim
21 words
The apparatus of claim 12 further comprising a post detection filter for filtering data that is output from the XNOR circuit.
Claim 16
Dependent Claim
16 words
The apparatus of claim 13 wherein the post detection filter comprises a two stage RC filter.
Claim 17
Dependent Claim
37 words
The apparatus of claim 14 further comprising a receive data correlator, a data body state machine and a variable divide counter for providing a received data signal from the filtered data received from the post detection filter.
Claim 18
Dependent Claim
35 words
The apparatus of claim 15 wherein the sampling flip-flop, the delay circuit, the XNOR circuit, the post detection filter, the correlator, the state machine and the counter are incorporated within a field programmable gate array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |