US5504030A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating high-density mask ROM devices
Assignee: United Microelectronics Corp
•
Filing: 1995-07-21
•
Granted: 1996-04-02
•
Expires: 2015-07-21
Abstract
Abstract A method of fabricating memory cells of a mask ROM device. A plurality of source/drain regions extending along a first direction is formed by implanting impurities into a semiconductor substrate, constituting bit lines of the memory cells. A code oxide layer is formed on a designated area of the semiconductor substrate defined by a barrier layer using a liquid-phase deposition process, whereby a multi-state mask ROM is fabricated by repeatedly performing the liquid-phase deposition process to form a series of coding oxide layers having increasing thicknesses. A gate oxide layer is formed on a portion of the semiconductor substrate not covered by the coding oxide layers. The thickness of the gate oxide layer is smaller than that of the coding oxide layers. A plurality of gate electrodes extending along a second direction orthogonal to the first direction is formed by depositing and patterning a conducting layer on the coding oxide layer and the gate oxide layer, constituting word lines of said memory cells. The cross area of every two adjacent bit lines and one word line thereby forms a memory cell of the mask ROM wherein threshold voltages of the memory cells are altered proportional to the thicknesses of the gate oxide layer and the coding oxide layers.
Inventors
- 👤 Chen-Hui Chung
- 👤 Kuan-Cheng Su
- 👤 Yi-Chung Sheng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 00:24
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/36; H10B20/367; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
215 words
A method for fabricating memory cells of a mask ROM device, comprising the steps of: forming a plurality of source/drain regions extending along a first direction by implanting impurities into a semiconductor substrate, said source/drain regions constituting bit lines of said memory cells; forming a barrier layer on said semiconductor substrate and patterning said barrier layer to form coding openings exposing areas of said semiconductor substrate between said bit lines; forming a coding oxide layer within said coding openings using a liquid-phase deposition process; removing said barrier layer; forming a gate oxide layer on a portion of said semiconductor substrate not covered by said coding oxide layer, said gate oxide layer having a thickness smaller than that of said coding oxide layer; and forming a conducting layer on said coding oxide layer and said gate oxide layer and patterning said conducting layer to form a plurality of gate electrodes extending along a second direction orthogonal to said first direction, said gate electrodes forming word lines of said memory cells, wherein a cross area of every two adjacent bit lines and one word line forms a memory cell of said mask ROM, the memory cell with said coding oxide layer having a threshold voltage larger than that of the memory cell without said coding oxide layer.
Claim 2
Independent Claim
215 words
A method for fabricating memory cells of a mask ROM device, comprising the steps of: forming a plurality of source/drain regions extending along a first direction by implanting impurities into a semiconductor substrate, said source/drain regions constituting bit lines of said memory cells; forming a barrier layer on said semiconductor substrate and patterning said barrier layer to form coding openings exposing areas of said semiconductor substrate between said bit lines; forming a coding oxide layer within said coding openings using a liquid-phase deposition process; removing said barrier layer; forming a gate oxide layer on a portion of said semiconductor substrate not covered by said coding oxide layer, said gate oxide layer having a thickness smaller than that of said coding oxide layer; and forming a conducting layer on said coding oxide layer and said gate oxide layer and patterning said conducting layer to form a plurality of gate electrodes extending along a second direction orthogonal to said first direction, said gate electrodes forming word lines of said memory cells, wherein a cross area of every two adjacent bit lines and one word line forms a memory cell of said mask ROM, the memory cell with said coding oxide layer having a threshold voltage larger than that of the memory cell without said coding oxide layer.
Claim 3
Dependent Claim
56 words
The method of fabricating memory cells of a mask ROM device according to claim 1, wherein the step of forming a barrier layer includes the step of forming a layer of photoresist on said semiconductor substrate and patterning said layer of photoresist to form coding openings exposing areas of said semiconductor substrate between said bit lines.
Claim 4
Dependent Claim
55 words
The method of fabricating memory cells of a mask ROM device according to claim 1, wherein the step of forming a conducting layer includes the step of forming a layer of polysilicon on said coding oxide layer and said gate oxide layer and patterning said layer of polysilicon to form said plurality of gate electrodes.
Claim 5
Dependent Claim
55 words
The method of fabricating memory cells of a mask ROM device according to claim 1, wherein the step of forming a conducting layer includes the step of forming a layer of polycide on said coding oxide layer and said gate oxide layer and patterning said layer of polycide to form said plurality of gate electrodes.
Claim 6
Independent Claim
217 words
A method of fabricating memory cells of a mask ROM device, comprising the steps of: forming a plurality of source/drain regions extending along a first direction by implanting impurities into a semiconductor substrate, said source/drain regions constituting bit lines of said memory cells; performing a plurality of liquid-phase deposition processes to form coding oxide layers with different thicknesses on designated areas of said semiconductor substrate defined by a series of barrier layers; forming a gate oxide layer with a thickness smaller than that of said coding oxide layers on a portion of said semiconductor substrate not covered by said coding oxide layers, wherein the thicknesses of said gate oxide and said coding oxide layers are in a relationship of an increasing series; and forming a conducting layer on said coding oxide layers and said gate oxide layer and patterning said conducting layer to form a plurality of gate electrodes extending along a second direction orthogonal to said first direction, said gate electrodes forming word lines of said memory cells, wherein a cross area of every two adjacent bit lines and one word line forms a memory cell of said mask ROM, said memory cell having threshold voltages of are altered to a degree proportional to the thicknesses of said gate oxide layer and said coding oxide layers.
Claim 7
Independent Claim
217 words
A method of fabricating memory cells of a mask ROM device, comprising the steps of: forming a plurality of source/drain regions extending along a first direction by implanting impurities into a semiconductor substrate, said source/drain regions constituting bit lines of said memory cells; performing a plurality of liquid-phase deposition processes to form coding oxide layers with different thicknesses on designated areas of said semiconductor substrate defined by a series of barrier layers; forming a gate oxide layer with a thickness smaller than that of said coding oxide layers on a portion of said semiconductor substrate not covered by said coding oxide layers, wherein the thicknesses of said gate oxide and said coding oxide layers are in a relationship of an increasing series; and forming a conducting layer on said coding oxide layers and said gate oxide layer and patterning said conducting layer to form a plurality of gate electrodes extending along a second direction orthogonal to said first direction, said gate electrodes forming word lines of said memory cells, wherein a cross area of every two adjacent bit lines and one word line forms a memory cell of said mask ROM, said memory cell having threshold voltages of are altered to a degree proportional to the thicknesses of said gate oxide layer and said coding oxide layers.
Claim 8
Dependent Claim
53 words
The method of fabricating memory cells of a mask ROM device according to claim 5, wherein the step of performing a plurality of liquid-phase deposition processes includes the step of performing the liquid-phase deposition processes three times to form three coding oxide layers with three different thicknesses, forming a 4-state mask ROM device.
Claim 9
Dependent Claim
42 words
The method of fabricating memory cells of a mask ROM device according to claim 5, wherein the step of performing a plurality of liquid-phase deposition processes includes the step of using layers of photoresist as masks to form said coding oxide layers.
Claim 10
Dependent Claim
55 words
The method of fabricating memory cells of a mask ROM device according to claim 5, wherein the step of forming a conducting layer includes the step of forming a layer of polysilicon on said coding oxide layer and said gate oxide layer and patterning said layer of polysilicon to form said plurality of gate electrodes.
Claim 11
Dependent Claim
55 words
The method of fabricating memory cells of a mask ROM device according to claim 5, wherein the step of forming a conducting layer includes the step of forming a layer of polycide on said coding oxide layer and said gate oxide layer and patterning said layer of polycide to form said plurality of gate electrodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |