Method and apparatus for clocking variable pixel frequencies and pixel depths in a memory display interface

Claim 2

A circuit for synchronizing pixel data being processed through a memory display interface, comprising: circuitry for sensing a pixel clock signal, the pixel clock signal synchronizing a plurality of color pixels for transfer over a pixel bus; circuitry for generating a pipeline clock signal synchronous with the pixel clock signal, the pipeline clock signal synchronizing a pixel processing pipeline including a plurality of pixel processing stages to propagate a plurality of pixels through the memory interface; circuitry for generating a shift clock signal, the shift clock signal enabling transfer of the plurality of pixels from a VRAM frame buffer to the memory display interface over a video bus; circuitry for sequencing the plurality of pixels into the pixel processing pipeline according to the frequency of the pixel clock signal and a predetermined pixel depth.

Claim 3

The circuit of claim 1, wherein the pixel clock is synchronized to a video clock, such that the video clock synchronizes video signals for a display device.

Claim 4

The circuit of claim 1, wherein the pipeline clock signal has a predetermined frequency m times the pixel clock, such that pixels are processed in parallel through the pixel processing pipeline for every c color pixels transferred in parallel over the pixel bus, wherein "m" and "c" are whole numbers.

Claim 5

The circuit of claim 1, wherein p of the pixels are transferred in parallel over the video bus for each of the shift clock signals, such that p is a nearest whole number equal to a predetermined video bus width divided by the predetermined pixel depth.

Claim 6

The circuit of claim 1, wherein the means for sequencing the pixels comprises: a plurality of signal buffers for receiving the pixels over the video bus; a plurality of data latches for storing the pixels, each data latch having an input and an output and a clock coupled to the pipeline clock; a plurality of multiplexers for selectively coupling the pixels and the outputs of the data latches to the inputs of the data latches according to an input select signal; multiplexer circuit coupled to receive the outputs of the data latches and feed the pixel processing pipeline.

Claim 9

The method of claim 6, wherein the pixel clock is synchronized to a video clock, such that the video clock synchronizes video signals for a display device.

Claim 10

The method of claim 6, wherein the pipeline clock has a frequency m times the pixel clock, such that pixels are processed in parallel through the pixel processing pipeline for every c color pixels transferred in parallel over the pixel bus, wherein "m" and "c" are whole numbers.

Claim 11

The method of claim 6, wherein p of the pixels are transferred in parallel over the video bus for each of the shift clock signals, such that p is a nearest whole number equal to a predetermined video bus width divided by the predetermined pixel depth.

Claim 12

A computer system comprising an error correction coding memory controller; a memory device, coupled to the error correction coding memory controller, for storing pixel data; a memory display interface, coupled to the memory device, for performing operations on the pixel data to generate color pixel data, the memory display interface including a circuit for synchronizing the pixel data being operated thereon, said circuit including circuitry for sensing a pixel clock signal, the pixel clock signal synchronizing the color pixel data being output from the memory display interface, circuitry for generating a pipeline clock signal synchronous with the pixel clock signal, the pipeline clock signal synchronizing a pixel processing pipeline including a plurality of pixel processing stages to propagate the pixel data through the memory display interface circuitry for generating a shift clock signal, the shift clock signal enabling transfer of the pixel data from a VRAM frame buffer to the memory display interface over a video bus, and circuitry for sequencing the pixel data into the pixel processing pipeline according to the frequency of the pixel clock signal and a predetermined pixel depth; a converter, coupled to the memory display interface, for converting the color pixel data into video signals; and a display, coupled to the converter, for receiving the video signals for display.

Claim 13

A computer system comprising an error correction coding memory controller; a memory device, coupled to the error correction coding memory controller, for storing pixel data; a memory display interface, coupled to the memory device, for performing operations on the pixel data to generate color pixel data, the memory display interface including a circuit for synchronizing the pixel data being operated thereon, said circuit including circuitry for sensing a pixel clock signal, the pixel clock signal synchronizing the color pixel data being output from the memory display interface, circuitry for generating a pipeline clock signal synchronous with the pixel clock signal, the pipeline clock signal synchronizing a pixel processing pipeline including a plurality of pixel processing stages to propagate the pixel data through the memory display interface circuitry for generating a shift clock signal, the shift clock signal enabling transfer of the pixel data from a VRAM frame buffer to the memory display interface over a video bus, and circuitry for sequencing the pixel data into the pixel processing pipeline according to the frequency of the pixel clock signal and a predetermined pixel depth; a converter, coupled to the memory display interface, for converting the color pixel data into video signals; and a display, coupled to the converter, for receiving the video signals for display.

Claim 14

The computer system of claim 10, wherein the pixel clock is synchronized to a video clock, such that the video clock synchronizes video signals for a display device.

Claim 15

The computer system of claim 10, wherein the pipeline clock signal has a predetermined frequency m times the pixel clock, such that pixels are processed in parallel through the pixel processing pipeline for every c color pixels transferred in parallel over the pixel bus, wherein "m" and "c" are whole numbers.

Claim 16

The computer system of claim 10, wherein p of the pixels are transferred in parallel over the video bus for each of the shift clock signals, such that p is a nearest whole number equal to a predetermined video bus width divided by the predetermined pixel depth.

Claim 17

The computer system of claim 10, wherein the means for sequencing the pixels comprises: a plurality of signal buffers for receiving the pixels over the video bus; a plurality of data latches for storing the pixels, each data latch having an input and an output and a clock coupled to the pipeline clock; a plurality of multiplexers for selectively coupling the pixels and the outputs of the data latches to the inputs of the data latches according to an input select signal; multiplexer circuit coupled to receive the outputs of the data latches and feed the pixel processing pipeline.

Claim 18

The computer system according to claim 10, wherein the memory device is a video random access memory device.

Claim 19

The computer system according to claim 15, wherein the converter is a digital to analog converter for generating the video signals being data and sync signals.