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US5502661A
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Checking design for testability rules with a VHDL simulator
Assignee: Siemens AG
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Filing: 1993-10-07
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Granted: 1996-03-26
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Expires: 2013-10-07
Abstract
Abstract Application of VHDL simulators to check the conformance of a design with Design for Testability (DFT) rules. A special DFT logic using VHDL's powerful logic modeling capabilities is defined and a kind of symbolic simulation based on this DFT logic is performed.
Inventors
- 👤 Wolfgang Glunz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:57
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/318357; G01R31/31704; G01R31/318364; G01R31/3185; G01R31/318533; G01R31/318583; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
148 words
A method for checking conformance of a digital circuit design with a given set of testability design rules, comprising the steps of: building a circuit description of the digital circuit design to be checked using a circuit description language that permits use of a user defined, non-standard logic; providing a circuit dependent sequence of stimuli using said circuit description language; providing a simulator which builds up a simulation model when said circuit description is loaded into it; applying the stimuli to the circuit description by loading the circuit description and the stimuli into the simulator and allowing the simulator to process the stimuli as applied to the circuit description until the simulator has no more events to process; and switching the simulator model into a check mode in which each component of the circuit checks a testability state and issues error messages if an illegal state was found.
Claim 2
Independent Claim
148 words
A method for checking conformance of a digital circuit design with a given set of testability design rules, comprising the steps of: building a circuit description of the digital circuit design to be checked using a circuit description language that permits use of a user defined, non-standard logic; providing a circuit dependent sequence of stimuli using said circuit description language; providing a simulator which builds up a simulation model when said circuit description is loaded into it; applying the stimuli to the circuit description by loading the circuit description and the stimuli into the simulator and allowing the simulator to process the stimuli as applied to the circuit description until the simulator has no more events to process; and switching the simulator model into a check mode in which each component of the circuit checks a testability state and issues error messages if an illegal state was found.
Claim 3
Dependent Claim
15 words
A method according to claim 1 wherein VHDL is used as said circuit description language.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-26 | 1999-09-25 | 2000-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-26 | 2003-09-25 | 2004-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-26 | 2007-09-25 | 2008-03-26 | $7700.00 | Window Closed / Lapsed |