Patent US2451253A successfully refreshed from Google Patents.
Patent US5502610A successfully refreshed from Google Patents.
US5502610A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Switching regulator having high current prevention features
Assignee: Microchip Technology Inc
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Filing: 1993-09-02
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Granted: 1996-03-26
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Expires: 2013-09-02
Abstract
Abstract A switching circuit has a pull-up FET and a pull-down FET coupled to a load circuit, each FET having a control terminal coupled to a current regulating circuit. The current regulating circuit provides a high predetermined current for a relatively short duration to the gates of the FETs to quickly turn on or turn off the FETs. After the short duration, a low quiescent current is applied to the gates to maintain the FETs in their present states. An inhibiting circuit, coupled between the pull-up FET and the pull-down FET, detects the states of the FETs and delays turn-on of one FET until the other FET has turned off. An overcurrent circuit monitors a current through a switching FET and turns off the FET after a predetermined time delay when an overcurrent condition is detected. The overcurrent circuit then turns on the FET after another predetermined time delay.
Inventors
- 👤 Steve I. Chaney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:52
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/38; G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; H02H; H02H7/00; H02H7/10; H02H7/12; H02H7/122; H02H7/1227; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/538; H02M7/53803
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
214 words
A switching circuit comprising: a first transistor having a first terminal for conducting load current to a load circuit, and a second terminal coupled to receive a first voltage; and a current regulating circuit, said current regulating circuit having an output terminal coupled to a control terminal of said first transistor, said current regulating circuit having an input terminal for receiving an input signal, said current regulating circuit comprising: a first current source for generating a first constant current; a second current source for generating a second constant current; one or more switches connected to said first current source, said second current source, and said control terminal of said first transistor; and a timer connected to said one or more switches for controlling said one or more switches to couple said first constant current to said control terminal of said first transistor for a first predetermined period of time in response to said input signal to switch said first transistor to a first state, and, after said first predetermined period of time, controlling said one or more switches to only couple said second constant current to said control terminal of said first transistor to maintain said first transistor in said first state, said second constant current being substantially less than said first constant current.
Claim 2
Dependent Claim
214 words
A switching circuit comprising: a first transistor having a first terminal for conducting load current to a load circuit, and a second terminal coupled to receive a first voltage; and a current regulating circuit, said current regulating circuit having an output terminal coupled to a control terminal of said first transistor, said current regulating circuit having an input terminal for receiving an input signal, said current regulating circuit comprising: a first current source for generating a first constant current; a second current source for generating a second constant current; one or more switches connected to said first current source, said second current source, and said control terminal of said first transistor; and a timer connected to said one or more switches for controlling said one or more switches to couple said first constant current to said control terminal of said first transistor for a first predetermined period of time in response to said input signal to switch said first transistor to a first state, and, after said first predetermined period of time, controlling said one or more switches to only couple said second constant current to said control terminal of said first transistor to maintain said first transistor in said first state, said second constant current being substantially less than said first constant current.
Claim 3
Dependent Claim
124 words
The switching circuit of claim 1 wherein said current regulating circuit further comprises: a pulse generator connected to said input terminal, said pulse generator for generating a pulse of a predetermined duration in response to said input signal received by said input terminal; and a switching circuit coupled to an output of said pulse generator for generating a first control signal during said pulse, said one or more switches being coupled to said switching circuit, said one or more switches connecting an output of said first current source to said control terminal of said first transistor in response to said first control signal, said one or more switches connecting an output of said second current source to said control terminal after said predetermined duration.
Claim 4
Dependent Claim
13 words
The switching circuit of claim 2 wherein said first transistor is a FET.
Claim 5
Dependent Claim
72 words
The switching circuit of claim 1 further comprising: a second transistor having a first terminal for conducting load current to said load circuit and a second terminal coupled to receive a second voltage; and an inhibiting circuit coupled to said first transistor and said second transistor, said inhibiting circuit detecting an on state of said second transistor and inhibiting turn-on of said first transistor until said second transistor has been turned off.
Claim 6
Dependent Claim
17 words
The switching circuit of claim 3 wherein said first transistor and said second transistor are both FETs.
Claim 7
Dependent Claim
69 words
The switching circuit of claim 1 further comprising: an overcurrent circuit coupled between said first terminal of said first transistor and said input terminal of said current regulator circuit, wherein when a current level detected by said overcurrent circuit exceeds a predetermined threshold value, said overcurrent circuit turns off said first transistor after a second predetermined period and turns back on said first transistor after a third predetermined period.
Claim 8
Dependent Claim
15 words
The switching circuit of claim 6 wherein said second predetermined period is approximately 4 μs.
Claim 9
Dependent Claim
13 words
The switching circuit of claim 1 wherein said first transistor is a FET.
Claim 10
Dependent Claim
176 words
The switching circuit of claim 1 wherein said current regulating circuit further comprises: a third current source for generating a third constant current, said third constant current being of a direction opposite to a direction of said first constant current; a fourth current source for generating a fourth constant current, said fourth constant current being of a direction opposite to a direction of said second constant current; said one or more switches being connected to said third current source and said fourth current source; said timer also for controlling said one or more switches to couple said third constant current to said control terminal of said first transistor for a second predetermined period in response to said input signal to switch said first transistor to a second state, and, after said second predetermined period, controlling said one or more switches to only couple said fourth constant current to said control terminal of said first transistor to maintain said first transistor in said second state, said fourth constant current being substantially less than said third constant current.
Claim 11
Dependent Claim
19 words
The switching circuit of claim 9 wherein said first predetermined period and said second predetermined period are the same.
Claim 12
Dependent Claim
301 words
A switching circuit comprising: a first transistor having a first terminal for conducting load current to a load circuit, and a second terminal coupled to receive a first voltage; a current regulating circuit, said current regulating circuit having an output terminal coupled to a control terminal of said first transistor, said current regulating circuit having an input terminal lot receiving an input signal, wherein said current regulating circuit provides a first current to said control terminal of said first transistor for a first period of time in response to said input signal to switch said first transistor to a first state, and wherein said current regulating circuit provides a second current to said first transistor control terminal after said first period of time to maintain said first transistor in said first state, said second current being substantially less than said first current; a second transistor having a first terminal for conducting load current to said load circuit and a second terminal coupled to receive a second voltage; and an inhibiting circuit coupled to said first transistor and said second transistor, said inhibiting circuit detecting an on state of said second transistor and inhibiting turn-on of said first transistor until said second transistor has been turned off, said inhibiting circuit comprising: a comparing circuit having a first input terminal, a second input terminal, and an output terminal, said comparing circuit receiving an input voltage on said first input terminal, a magnitude of said input voltage corresponding to a state of said second transistor; and a voltage source coupled to said second input terminal of said comparing circuit, said voltage source supplying a fixed reference voltage, wherein said comparing circuit outputs at said output terminal a first signal for inhibiting turn-on of said first transistor when said input voltage exceeds said reference voltage.
Claim 13
Dependent Claim
301 words
A switching circuit comprising: a first transistor having a first terminal for conducting load current to a load circuit, and a second terminal coupled to receive a first voltage; a current regulating circuit, said current regulating circuit having an output terminal coupled to a control terminal of said first transistor, said current regulating circuit having an input terminal lot receiving an input signal, wherein said current regulating circuit provides a first current to said control terminal of said first transistor for a first period of time in response to said input signal to switch said first transistor to a first state, and wherein said current regulating circuit provides a second current to said first transistor control terminal after said first period of time to maintain said first transistor in said first state, said second current being substantially less than said first current; a second transistor having a first terminal for conducting load current to said load circuit and a second terminal coupled to receive a second voltage; and an inhibiting circuit coupled to said first transistor and said second transistor, said inhibiting circuit detecting an on state of said second transistor and inhibiting turn-on of said first transistor until said second transistor has been turned off, said inhibiting circuit comprising: a comparing circuit having a first input terminal, a second input terminal, and an output terminal, said comparing circuit receiving an input voltage on said first input terminal, a magnitude of said input voltage corresponding to a state of said second transistor; and a voltage source coupled to said second input terminal of said comparing circuit, said voltage source supplying a fixed reference voltage, wherein said comparing circuit outputs at said output terminal a first signal for inhibiting turn-on of said first transistor when said input voltage exceeds said reference voltage.
Claim 14
Dependent Claim
17 words
The switching circuit of claim 4 wherein said first transistor and said second transistor are both FETs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-26 | 1999-09-25 | 2000-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-26 | 2003-09-25 | 2004-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-26 | 2007-09-25 | 2008-03-26 | $7700.00 | Window Closed / Lapsed |