US5501996A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacture of high coupling ratio single polysilicon floating gate EPROM or EEPROM cell
Assignee: United Microelectronics Corp
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Filing: 1994-12-14
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Granted: 1996-03-26
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Expires: 2014-12-14
Abstract
Abstract A MOSFET semiconductor, erasable programmable ROM device on a lightly doped semiconductor substrate comprising field oxide regions in the semiconductor substrate. The field oxide regions extends down into sunken regions in the substrate through the openings. At least one of the field oxide regions is removed from the substrate to provide an opened one of the sunken regions in the substrate below the removed one of the field oxide regions. Ion implanted regions lie in the substrate below the openings. A gate oxide layer over the opened sunken region, and a floating gate over the gate oxide layer. Preferably, a tunnel oxide region is formed on the surface of the device with the floating gate overlying the tunnel oxide region to form an EEPROM device. The exposed sunken region has a V-shaped cross section sunken region extending deep into the substrate.
Inventors
- 👤 Sheng-Hsing Yang
- 👤 Jyh-Kuang Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:16
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B41/60; Y; Y10; Y10S; Y10S148/00; Y10S148/168
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
136 words
A method of manufacturing an erasable programmable ROM device on a lightly doped semiconductor substrate having a surface, said method comprising the sequence of steps as follows: forming a mask upon said substrate with openings therein, forming regions of silicon dioxide in said semiconductor substrate through said openings in said mask, said regions of silicon dioxide extending down into sunken regions in said substrate, removing said silicon dioxide from said substrate forming at least one opening in a sunken region in said substrate, introduction of ions into said substrate below said sunken region to form a buried control gate conductor region in said substrate, forming a gate oxide layer over said buried control gate conductor region in said substrate, and forming a gate structure over said gate oxide layer to form said erasable programmable ROM device.
Claim 2
Independent Claim
136 words
A method of manufacturing an erasable programmable ROM device on a lightly doped semiconductor substrate having a surface, said method comprising the sequence of steps as follows: forming a mask upon said substrate with openings therein, forming regions of silicon dioxide in said semiconductor substrate through said openings in said mask, said regions of silicon dioxide extending down into sunken regions in said substrate, removing said silicon dioxide from said substrate forming at least one opening in a sunken region in said substrate, introduction of ions into said substrate below said sunken region to form a buried control gate conductor region in said substrate, forming a gate oxide layer over said buried control gate conductor region in said substrate, and forming a gate structure over said gate oxide layer to form said erasable programmable ROM device.
Claim 3
Dependent Claim
13 words
A method in accordance with claim 1 wherein said mask comprises silicon nitride.
Claim 4
Dependent Claim
26 words
A method in accordance with claim 2 wherein said mask is formed over a pad oxide on said substrate and said substrate comprises lightly doped silicon.
Claim 5
Dependent Claim
14 words
A method in accordance with claim 3 wherein said silicon dioxide comprises field oxide.
Claim 6
Dependent Claim
25 words
A method in accordance with claim 4 wherein said field oxide is removed by etching, thereby exposing said sunken region for said control gate region.
Claim 7
Dependent Claim
29 words
A method in accordance with claim 5 wherein said substrate is etched through said exposed sunken region forming a V-shaped cross section sunken region extending deeper into said substrate.
Claim 8
Dependent Claim
35 words
A method in accordance with claim 6 wherein a tunnel oxide region is formed on said surface of said semiconductor substrate with said gate structure overlying said tunnel oxide region to form an EEPROM device.
Claim 9
Dependent Claim
20 words
A method in accordance with claim 7 wherein said introduction of ions into said substrate is performed by ion implantation.
Claim 10
Dependent Claim
35 words
A method in accordance with claim 1 wherein a tunnel oxide region is formed on said surface of said semiconductor substrate with said gate structure overlying said tunnel oxide region to form an EEPROM device.
Claim 11
Dependent Claim
17 words
A method in accordance with claim 9 wherein said regions of silicon dioxide comprise a field oxide.
Claim 12
Independent Claim
141 words
A method of manufacturing an erasable programmable ROM device on a lightly doped semiconductor substrate having a surface, said method comprising the sequence of steps as follows: forming a pad oxide layer on said substrate, forming a mask upon said substrate with openings therein, forming field oxide regions in said semiconductor substrate, said field oxide regions extending down into sunken regions in said substrate through said openings in said mask, removing at least one of said field oxide regions from said substrate to provide an opened one of said sunken regions in said substrate below said removed one of said field oxide regions, introducing ions into said substrate through said openings in said mask to form a buried control gate region, forming a gate oxide layer over said opened sunken region, and forming a gate layer over said gate oxide layer.
Claim 13
Independent Claim
141 words
A method of manufacturing an erasable programmable ROM device on a lightly doped semiconductor substrate having a surface, said method comprising the sequence of steps as follows: forming a pad oxide layer on said substrate, forming a mask upon said substrate with openings therein, forming field oxide regions in said semiconductor substrate, said field oxide regions extending down into sunken regions in said substrate through said openings in said mask, removing at least one of said field oxide regions from said substrate to provide an opened one of said sunken regions in said substrate below said removed one of said field oxide regions, introducing ions into said substrate through said openings in said mask to form a buried control gate region, forming a gate oxide layer over said opened sunken region, and forming a gate layer over said gate oxide layer.
Claim 14
Dependent Claim
13 words
A method in accordance with claim 11 wherein said mask comprises silicon nitride.
Claim 15
Dependent Claim
26 words
A method in accordance with claim 12 wherein said mask is formed over a pad oxide on said substrate and said substrate comprises lightly doped silicon.
Claim 16
Dependent Claim
35 words
A method in accordance with claim 13 wherein a tunnel oxide region is formed on said surface of said semiconductor substrate with said gate layer overlying said tunnel oxide region to form an EEPROM device.
Claim 17
Dependent Claim
20 words
A method in accordance with claim 14 wherein said field oxide is removed by etching, thereby exposing said sunken regions.
Claim 18
Dependent Claim
29 words
A method in accordance with claim 15 wherein said substrate is etched through said exposed sunken region forming a V-shaped cross section sunken region extending deeper into said substrate.
Claim 19
Dependent Claim
25 words
A method in accordance with claim 16 wherein said substrate is etched with an aqueous KOH solution to form said V-shaped cross section sunken region.
Claim 20
Dependent Claim
20 words
A method in accordance with claim 17 wherein said introduction of ions into said substrate is performed by ion implantation.
Claim 21
Dependent Claim
42 words
A method in accordance with claim 11 wherein said substrate is etched through said exposed sunken region forming a V-shaped cross section sunken region extending deeper into said substrate with an aqueous KOH solution to form said V-shaped cross section sunken region.
Claim 22
Dependent Claim
35 words
A method in accordance with claim 19 wherein a tunnel oxide region is formed on said surface of said semiconductor substrate with said gate layer overlying said tunnel oxide region to form an EEPROM device.
Claim 23
Independent Claim
251 words
A method of manufacturing an EEPROM memory device on a lightly doped semiconductor substrate having a surface, said method comprising the sequence of steps as follows: forming a first oxide layer on said substrate, forming a silicon nitride mask upon said first oxide layer with openings therein, forming openings in said silicon nitride mask, etching through said openings in said silicon nitride mask down to said semiconductor substrate, forming field oxide regions in portions of said semiconductor substrate exposed through said silicon nitride mask, said field oxide regions extending down into sunken regions in said substrate through said openings in said mask, removing at least one of said field oxide regions from said substrate to provide an opened one of said sunken regions in said substrate below said removed one of said field oxide regions, introducing ions into said substrate through said openings in said mask, removing said silicon nitride mask, removing said first oxide layer exposing said surface of said substrate aside from said field oxide regions, and forming a gate oxide layer over said surface of said substrate including the surface of said opened sunken region, forming a mask with tunnel oxide mask opening over said gate oxide layer, etching a tunnel oxide opening through said tunnel oxide mask opening down to said surface of said substrate, forming a tunnel oxide layer through said tunnel oxide mask opening on said surface of said substrate, and forming a gate structure over said gate oxide layer and said tunnel oxide layer.
Claim 24
Independent Claim
251 words
A method of manufacturing an EEPROM memory device on a lightly doped semiconductor substrate having a surface, said method comprising the sequence of steps as follows: forming a first oxide layer on said substrate, forming a silicon nitride mask upon said first oxide layer with openings therein, forming openings in said silicon nitride mask, etching through said openings in said silicon nitride mask down to said semiconductor substrate, forming field oxide regions in portions of said semiconductor substrate exposed through said silicon nitride mask, said field oxide regions extending down into sunken regions in said substrate through said openings in said mask, removing at least one of said field oxide regions from said substrate to provide an opened one of said sunken regions in said substrate below said removed one of said field oxide regions, introducing ions into said substrate through said openings in said mask, removing said silicon nitride mask, removing said first oxide layer exposing said surface of said substrate aside from said field oxide regions, and forming a gate oxide layer over said surface of said substrate including the surface of said opened sunken region, forming a mask with tunnel oxide mask opening over said gate oxide layer, etching a tunnel oxide opening through said tunnel oxide mask opening down to said surface of said substrate, forming a tunnel oxide layer through said tunnel oxide mask opening on said surface of said substrate, and forming a gate structure over said gate oxide layer and said tunnel oxide layer.
Claim 25
Independent Claim
243 words
A method of manufacturing an erasable programmable EEPROM device on a lightly doped semiconductor substrate having a surface, said method comprising the sequence of steps as follows: forming a pad oxide layer on said substrate, forming a first mask upon said pad oxide layer with openings therein, forming openings in said first mask, etching through said openings in said first mask down to said semiconductor substrate, forming field oxide regions in portions of said semiconductor substrate exposed through said first mask, said field oxide regions extending down into sunken regions in said substrate through said openings in said first mask, removing at least one of said field oxide regions from said substrate to provide an opened one of said sunken regions in said substrate below said removed one of said field oxide regions, introducing ions into said substrate through said openings in said first mask, removing said first mask, removing said pad oxide layer exposing said surface of said substrate, forming a gate oxide layer over said surface of said substrate including the surface of said opened sunken region, forming a mask with tunnel oxide mask opening over said gate oxide layer, etching a tunnel oxide opening through said tunnel oxide mask opening down to said surface of said substrate, forming a tunnel oxide layer through said tunnel oxide mask opening on said surface of said substrate, forming a floating gate structure over said gate oxide layer and over said tunnel oxide layer.
Claim 26
Independent Claim
243 words
A method of manufacturing an erasable programmable EEPROM device on a lightly doped semiconductor substrate having a surface, said method comprising the sequence of steps as follows: forming a pad oxide layer on said substrate, forming a first mask upon said pad oxide layer with openings therein, forming openings in said first mask, etching through said openings in said first mask down to said semiconductor substrate, forming field oxide regions in portions of said semiconductor substrate exposed through said first mask, said field oxide regions extending down into sunken regions in said substrate through said openings in said first mask, removing at least one of said field oxide regions from said substrate to provide an opened one of said sunken regions in said substrate below said removed one of said field oxide regions, introducing ions into said substrate through said openings in said first mask, removing said first mask, removing said pad oxide layer exposing said surface of said substrate, forming a gate oxide layer over said surface of said substrate including the surface of said opened sunken region, forming a mask with tunnel oxide mask opening over said gate oxide layer, etching a tunnel oxide opening through said tunnel oxide mask opening down to said surface of said substrate, forming a tunnel oxide layer through said tunnel oxide mask opening on said surface of said substrate, forming a floating gate structure over said gate oxide layer and over said tunnel oxide layer.
Claim 27
Dependent Claim
14 words
A method in accordance with claim 22 wherein said first mask comprises silicon nitride.
Claim 28
Dependent Claim
26 words
A method in accordance with claim 23 wherein said mask is formed over a pad oxide on said substrate and said substrate comprises lightly doped silicon.
Claim 29
Dependent Claim
20 words
A method in accordance with claim 24 wherein said field oxide is removed by etching, thereby exposing said sunken regions.
Claim 30
Dependent Claim
29 words
A method in accordance with claim 25 wherein said substrate is etched through said exposed sunken region forming a V-shaped cross section sunken region extending deeper into said substrate.
Claim 31
Dependent Claim
25 words
A method in accordance with claim 26 wherein said substrate is etched with an aqueous KOH solution to form said V-shaped cross section sunken region.
Claim 32
Dependent Claim
20 words
A method in accordance with claim 27 wherein said introduction of ions into said substrate is performed by ion implantation.
Claim 33
Dependent Claim
42 words
A method in accordance with claim 22 wherein said substrate is etched through said exposed sunken region forming a V-shaped cross section sunken region extending deeper into said substrate with an aqueous KOH solution to form said V-shaped cross section sunken region.
Claim 34
Dependent Claim
35 words
A method in accordance with claim 29 wherein a tunnel oxide region is formed on said surface of said semiconductor substrate with said floating gate overlying said tunnel oxide region to form an EEPROM device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-03-26 | 1999-09-25 | 2000-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-26 | 2003-09-25 | 2004-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-26 | 2007-09-25 | 2008-03-26 | $7700.00 | Window Closed / Lapsed |