US5500945A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for controlling a system bus of a multiprocessor system
Assignee: Fujitsu Ltd
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Filing: 1995-07-31
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Granted: 1996-03-19
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Expires: 2015-07-31
Abstract
Abstract In a bus arbiter connected to a system bus of a multi-processor system having a plurality of modules respectively having processors, a first unit detects an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferred via the system bus. A second unit initializes the internal state of the bus arbiter to restart the bus arbiter when the first unit detects an abnormality.
Inventors
- 👤 Ikuo Maeda
- 👤 Hirohide Sugahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:56
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/0706; G06F11/0721; G06F11/0724; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
130 words
A bus arbiter connected to a system bus of a multi-processor system, a plurality of modules respectively having processors being connected to the system bus, said bus arbiter comprising: first means for detecting an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferred via the system bus; second means for initializing the internal state of the bus arbiter to restart the bus arbiter when said first means detects the abnormality; and third means for determining whether or not said first means detects another abnormality within a period of time after said first means detects the abnormality and for stopping an operation of the system bus when said first means detects said another abnormality within the period of time.
Claim 2
Dependent Claim
130 words
A bus arbiter connected to a system bus of a multi-processor system, a plurality of modules respectively having processors being connected to the system bus, said bus arbiter comprising: first means for detecting an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferred via the system bus; second means for initializing the internal state of the bus arbiter to restart the bus arbiter when said first means detects the abnormality; and third means for determining whether or not said first means detects another abnormality within a period of time after said first means detects the abnormality and for stopping an operation of the system bus when said first means detects said another abnormality within the period of time.
Claim 3
Dependent Claim
71 words
The bus arbiter as claimed in claim 1, wherein said first means comprises: means for performing a first parity check operation on the predetermined signal transferred via the system bus and a second parity check operation on information regarding the internal state of the bus arbiter; and means for detecting the abnormality by comparing the result of the first parity check operation with the result of the second parity check operation.
Claim 4
Dependent Claim
135 words
A multi-processor system comprising: a bus arbiter; a plurality of modules respectively having processors; and a system bus to which said bus arbiter and said plurality of modules are connected, said bus arbiter comprising: first means for determining an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferred via the system bus; second means for initializing the internal state of the bus arbiter to restart the bus arbiter when said first means detects the abnormality; and third means for determining whether or not said first means detects another abnormality within a period of time after said first means detects the abnormality and for stopping an operation of the system bus when said first means detects said another abnormality within the period of time.
Claim 5
Dependent Claim
135 words
A multi-processor system comprising: a bus arbiter; a plurality of modules respectively having processors; and a system bus to which said bus arbiter and said plurality of modules are connected, said bus arbiter comprising: first means for determining an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferred via the system bus; second means for initializing the internal state of the bus arbiter to restart the bus arbiter when said first means detects the abnormality; and third means for determining whether or not said first means detects another abnormality within a period of time after said first means detects the abnormality and for stopping an operation of the system bus when said first means detects said another abnormality within the period of time.
Claim 6
Dependent Claim
71 words
The multi-processor system as claimed in claim 3, wherein said first means comprises; means for performing a first parity check operation on the predetermined signal transferred via the system bus and a second parity check operation on information regarding the internal state of the bus arbiter; and means for detecting an abnormality by comparing the result of the first parity check operation with the result of the second parity check operation.
Claim 7
Independent Claim
118 words
A method of controlling, by means of a bus arbiter, a system bus of a multi-processor system and a plurality of modules respectively having processors being connected to the system bus, said method comprising the steps of: detecting an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferred via the system bus; initializing the internal state of the bus arbiter to restart the bus arbiter when the abnormality is detected; determining whether or not another abnormality is detected within a period of time after the abnormality is detected; stopping an operation of the system bus when said another abnormality is detected within the period of time.
Claim 8
Independent Claim
118 words
A method of controlling, by means of a bus arbiter, a system bus of a multi-processor system and a plurality of modules respectively having processors being connected to the system bus, said method comprising the steps of: detecting an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferred via the system bus; initializing the internal state of the bus arbiter to restart the bus arbiter when the abnormality is detected; determining whether or not another abnormality is detected within a period of time after the abnormality is detected; stopping an operation of the system bus when said another abnormality is detected within the period of time.
Claim 9
Dependent Claim
70 words
The method as claimed in claim 5, wherein said step of detecting comprises the steps of: performing a first parity check operation on the predetermined signal transferred via the system bus and a second parity check operation on information regarding the internal state of the bus arbiter; and detecting the abnormality by comparing the result of the first parity check operation with the result of the second parity check operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-19 | 1999-09-18 | 2000-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-19 | 2003-09-18 | 2004-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-19 | 2007-09-18 | 2008-03-19 | $7700.00 | Window Closed / Lapsed |