US5500384A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a bit line via hole in a memory cell
Assignee: Qimonda AG
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Filing: 1994-08-23
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Granted: 1996-03-19
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Expires: 2014-08-23
Abstract
Abstract An improved method for manufacturing a bit line via hole for a memory cell is disclosed wherein changes in the topography of a conductive layer forming the cell plate that are caused by the capacitor are utilized for producing an etching mask for the bit line via hole. A depression is formed because the second source/drain region of the transistor which is to be contacted by the bit line is not covered by the lower capacitor plate. The etching mask is not produced in the depression but only at the raised locations and is therefore self-aligned above the second S/D region.
Inventors
- 👤 Hanno Melzner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:37
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
132 words
A method for manufacturing a bit line via hole of a memory cell, wherein a transistor of the memory cell is comprised of first and second source/drain regions and a gate region, the first source/drain region being connected to a lower capacitor plate and the second source/drain region having a space above its surface, said method comprising the steps of: applying a conductive layer over the space above the second source/drain region and lower capacitor plate to form a depressed portion of the conductive layer over the second source/drain region; applying a self-aligned bit line via hole mask, which is self-aligned relative to the second source/drain region, to the conductive layer other than at the depressed portion; and etching a bit line via hole in the depressed portion of the conductive layer.
Claim 2
Independent Claim
132 words
A method for manufacturing a bit line via hole of a memory cell, wherein a transistor of the memory cell is comprised of first and second source/drain regions and a gate region, the first source/drain region being connected to a lower capacitor plate and the second source/drain region having a space above its surface, said method comprising the steps of: applying a conductive layer over the space above the second source/drain region and lower capacitor plate to form a depressed portion of the conductive layer over the second source/drain region; applying a self-aligned bit line via hole mask, which is self-aligned relative to the second source/drain region, to the conductive layer other than at the depressed portion; and etching a bit line via hole in the depressed portion of the conductive layer.
Claim 3
Dependent Claim
45 words
The method for manufacturing a bit line via hole of a memory cell of claim 1, wherein the space above the second source/drain region is formed as a result of a spacing formed between the lower capacitor plate and a capacitor of an adjacent cell.
Claim 4
Dependent Claim
39 words
The method for manufacturing a bit line via hole of a memory cell of claim 1, further comprising the step of forming an auxiliary structure exclusively on the depressed portion prior to etching of the bit line via hole.
Claim 5
Dependent Claim
31 words
The method for manufacturing a bit line via hole of a memory cell of claim 3, wherein the step of forming the auxiliary structure includes forming and etching a planarizing layer.
Claim 6
Dependent Claim
35 words
The method for manufacturing a bit line via hole of a memory cell of claim 4, wherein the step of forming the auxiliary structure further includes forming an auxiliary layer comprising a temperature resistant material.
Claim 7
Dependent Claim
42 words
The method for manufacturing a bit line via hole of a memory cell of claim 5, wherein the step of applying the mask is comprised of thermally treating a surface of the conductive layer which is not covered by the auxiliary structure.
Claim 8
Independent Claim
178 words
A method for manufacturing a bit line via hole of a memory cell, wherein a transistor of the memory cell is comprised of first and second source/drain regions and a gate region, the first source/drain region being connected to a lower capacitor plate, said method comprising the steps of: applying a conductive layer over the second source/drain region and lower capacitor plate to form a depressed portion of the conductive layer over the second source/drain region; applying a silicon nitride layer over the conductive layer; applying a planarizing layer over the silicon nitride layer and etching the planarizing layer to form a resist plug above the depressed portion; selectively etching the silicon nitride layer and removing the resist plug to provide an auxiliary structure of silicon nitride which covers a surface of the depressed portion; and applying an etching mask over the conductive layer and removing the auxiliary structure of silicon nitride and subsequently etching an exposed portion of the conductive layer to expose a surface of the second source/drain region to form a bit line via hole.
Claim 9
Independent Claim
178 words
A method for manufacturing a bit line via hole of a memory cell, wherein a transistor of the memory cell is comprised of first and second source/drain regions and a gate region, the first source/drain region being connected to a lower capacitor plate, said method comprising the steps of: applying a conductive layer over the second source/drain region and lower capacitor plate to form a depressed portion of the conductive layer over the second source/drain region; applying a silicon nitride layer over the conductive layer; applying a planarizing layer over the silicon nitride layer and etching the planarizing layer to form a resist plug above the depressed portion; selectively etching the silicon nitride layer and removing the resist plug to provide an auxiliary structure of silicon nitride which covers a surface of the depressed portion; and applying an etching mask over the conductive layer and removing the auxiliary structure of silicon nitride and subsequently etching an exposed portion of the conductive layer to expose a surface of the second source/drain region to form a bit line via hole.
Claim 10
Dependent Claim
24 words
The method for manufacturing a bit line via hole of a memory cell of claim 7, wherein the lower capacitor plate is crown shaped.
Claim 11
Dependent Claim
22 words
The method for manufacturing a bit line via hole of a memory cell of claim 7, wherein the planarizing layer is photoresist.
Claim 12
Dependent Claim
23 words
The method for manufacturing a bit line via hole of a memory cell of claim 7, wherein the conductive layer is doped silicon.
Claim 13
Dependent Claim
34 words
The method for manufacturing a bit line via hole of a memory cell of claim 7, further comprising an additional step of providing an edge insulation on an uncovered edge of the conductive layer.
Claim 14
Dependent Claim
23 words
The method for manufacturing a bit line via hole of a memory cell of claim 11, wherein the edge insulation is a spacer.
Claim 15
Dependent Claim
28 words
The method for manufacturing a bit line via hole of a memory cell of claim 11, wherein said step of providing edge insulation includes oxidizing the conductive layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-19 | 1999-09-18 | 2000-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-19 | 2003-09-18 | 2004-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-19 | 2007-09-18 | 2008-03-19 | $7700.00 | Window Closed / Lapsed |