EP0478262A1
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Random access memory device and process of fabrication thereof
Assignee: NEC Corp
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Filing: 1991-09-23
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Granted: —
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Expires: 2011-09-23
Abstract
Abstract A random access memory device comprises a plurality of memory cells each having a transfer field effect transistor (26a/26b/24/25a) and a stacked type storage capacitor (28/30/31). A first inter-level insulating film (27) is provided between the transfer field effect transistor and the stacked type storage capacitor. A peripheral circuit has a plurality of component transistors, and each of the component transistors (26c/24/25c/32b/34) has source and drain regions (26c/34) of an LDD (lightly-doped drain) structure. The LDD structure is formed by using side walls (32b) made from an insulating film used for the first inter-level insulating film after the formation of the stacked type storage capacitor so that the source region (26b) of the transfer field effect transistor is not damaged by bombardment in an anisotropical etching for forming the side walls.
Inventors
- 👤 Takanori c/o NEC Corporation Saeki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 14:05
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/05
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
386 words
A random access memory device fabricated on a single semiconductor substrate (21;41;61) of a first conductivity type, comprising: a) a plurality of memory cells; and b) at least one component field effect transistor formed a part of a peripheral circuit, characterized in that each of said plurality of memory cells comprises a-1) a transfer field effect transistor having first and second impurity regions ( 26b/26a; 47b/47a; 67b/67a) of a second conductivity type spaced apart from each other by a first channel forming region, a first gate insulating film (24;44;64) formed on said first channel forming region, and a first gate structure (25a; 46a; 66a) formed on said first gate insulating film, a-2) a first inter-level insulating film (27;48;68) covering said first gate structure and exposing said first and second impurity regions, and a-3) a staked type storage capacitor having a lower electrode (28;50;70) formed on said first inter-level insulating film and held in contact with said first impurity region, a dielectric film structure (30;52;72) covering said lower electrode, and an upper electrode (31;53;70) held in contact with said dielectric film structure, and in that said at least one component field effect transistor comprises b-1) third and fourth impurity regions of said second conductivity type spaced apart from each other by a second channel forming region, each of said third and fourth impurity regions being implemented by a lightly doped impurity sub-region (26c; 47c; 67c) partially overlapped with a heavily doped impurity sub-region (34;55a; 75a), b-2) a second gate insulating film (24; 44; 64) formed on said second channel forming region, and b-3) a second gate structure (25c; 46c; 66c) formed on said second gate insulating film and having side walls (32b; 49c; 69c) on side surfaces thereof, said side walls being made from an insulating film used for said first inter-level insulating film, said random access memory device further comprising c) an upper inter-level insulating film structure (35/37; 56/58; 76/79/82) covering said plurality of memory cells and said at least one component field effect transistor and having contact holes exposing said second impurity region and one of said third and fourth impurity regions, and d) conductive wring strips (36/38; 57/59; 81/80a/83/84) passing through said contact holes and held in contact with said second impurity region and said one of said third and fourth impurity regions, respectively.
Claim 2
Dependent Claim
386 words
A random access memory device fabricated on a single semiconductor substrate (21;41;61) of a first conductivity type, comprising: a) a plurality of memory cells; and b) at least one component field effect transistor formed a part of a peripheral circuit, characterized in that each of said plurality of memory cells comprises a-1) a transfer field effect transistor having first and second impurity regions ( 26b/26a; 47b/47a; 67b/67a) of a second conductivity type spaced apart from each other by a first channel forming region, a first gate insulating film (24;44;64) formed on said first channel forming region, and a first gate structure (25a; 46a; 66a) formed on said first gate insulating film, a-2) a first inter-level insulating film (27;48;68) covering said first gate structure and exposing said first and second impurity regions, and a-3) a staked type storage capacitor having a lower electrode (28;50;70) formed on said first inter-level insulating film and held in contact with said first impurity region, a dielectric film structure (30;52;72) covering said lower electrode, and an upper electrode (31;53;70) held in contact with said dielectric film structure, and in that said at least one component field effect transistor comprises b-1) third and fourth impurity regions of said second conductivity type spaced apart from each other by a second channel forming region, each of said third and fourth impurity regions being implemented by a lightly doped impurity sub-region (26c; 47c; 67c) partially overlapped with a heavily doped impurity sub-region (34;55a; 75a), b-2) a second gate insulating film (24; 44; 64) formed on said second channel forming region, and b-3) a second gate structure (25c; 46c; 66c) formed on said second gate insulating film and having side walls (32b; 49c; 69c) on side surfaces thereof, said side walls being made from an insulating film used for said first inter-level insulating film, said random access memory device further comprising c) an upper inter-level insulating film structure (35/37; 56/58; 76/79/82) covering said plurality of memory cells and said at least one component field effect transistor and having contact holes exposing said second impurity region and one of said third and fourth impurity regions, and d) conductive wring strips (36/38; 57/59; 81/80a/83/84) passing through said contact holes and held in contact with said second impurity region and said one of said third and fourth impurity regions, respectively.
Claim 3
Dependent Claim
307 words
2 A process of fabricating a random access memory device, comprising the steps of: a) preparing a semiconductor substrate (21;41;61) of a first conductivity type; b) forming first and second gate structures (25a/25c; 66a/66c; 66a/66c) on first and second gate insulating films, respectively; and c) forming first, second, third and fourth lightly doped impurity regions (26b/26a/26c; 47b/47a/47c; 67b/67a/67c) of a second conductivity type in a self-aligned manner using said first and second gate structures as an ion-implanting mask, said second conductivity type being opposite to said first conductivity type, a transfer field effect transistor with said first gate structure being completed, characterized by the steps of d) covering said first and second gate structures with a first inter-level insulating film (27/48;68); e) forming a stacked type storage capacitor (28/30;31; 50/52;53; 70/72/73) provided on said first inter-level insulating film and held in contact with said first lightly doped impurity region; f) anisotropically etching said first inter-level insulating film covering said second gate structure so that side walls (32b;49c; 69b) are formed on side surfaces of said second gate structure; g) forming heavily doped impurity regions (34; 55a; 75a) of said second conductivity type in a self-aligned manner using said second gate structure and said side walls as an ion-implanting mask, said heavily doped impurity regions partially overlapped with said third and fourth lightly doped impurity regions, respectively, thereby completing a component field effect transistor forming a part of a peripheral circuit; h) completing an upper inter-level insulating film structure (35/37; 56/58; 76/79/82) covering said transfer field effect transistor, said stacked type storage capacitor and said component field effect transistor; and i) completing conductive wiring strips (36/38; 57/59; 80a/81/83/84) respectively held in contact with said second lightly doped impurity region and one of said heavily doped impurity regions through respective contact holes formed in said upper inter-level insulating film.
Claim 4
Dependent Claim
307 words
2 A process of fabricating a random access memory device, comprising the steps of: a) preparing a semiconductor substrate (21;41;61) of a first conductivity type; b) forming first and second gate structures (25a/25c; 66a/66c; 66a/66c) on first and second gate insulating films, respectively; and c) forming first, second, third and fourth lightly doped impurity regions (26b/26a/26c; 47b/47a/47c; 67b/67a/67c) of a second conductivity type in a self-aligned manner using said first and second gate structures as an ion-implanting mask, said second conductivity type being opposite to said first conductivity type, a transfer field effect transistor with said first gate structure being completed, characterized by the steps of d) covering said first and second gate structures with a first inter-level insulating film (27/48;68); e) forming a stacked type storage capacitor (28/30;31; 50/52;53; 70/72/73) provided on said first inter-level insulating film and held in contact with said first lightly doped impurity region; f) anisotropically etching said first inter-level insulating film covering said second gate structure so that side walls (32b;49c; 69b) are formed on side surfaces of said second gate structure; g) forming heavily doped impurity regions (34; 55a; 75a) of said second conductivity type in a self-aligned manner using said second gate structure and said side walls as an ion-implanting mask, said heavily doped impurity regions partially overlapped with said third and fourth lightly doped impurity regions, respectively, thereby completing a component field effect transistor forming a part of a peripheral circuit; h) completing an upper inter-level insulating film structure (35/37; 56/58; 76/79/82) covering said transfer field effect transistor, said stacked type storage capacitor and said component field effect transistor; and i) completing conductive wiring strips (36/38; 57/59; 80a/81/83/84) respectively held in contact with said second lightly doped impurity region and one of said heavily doped impurity regions through respective contact holes formed in said upper inter-level insulating film.
References Cited (Backward Citations)
EP0191612A2
Cited
DE4034169A1
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