Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus

Claim 2

An information processing system, comprising: a system bus having connected thereto a central processing unit (CPU); a peripheral bus having connected thereto a master peripheral device which initiates transactions over said peripheral bus in which data is transferred between said master peripheral device and a slave peripheral device connected to said peripheral bus, said master peripheral device able to detect parity errors occurring during said transactions, set a status register and re-initiate transactions if a parity error is detected, and reset said status register if a re-initiated transaction is successfully transacted without an occurrence of a parity error; a host bridge connecting said system bus to said peripheral bus for simultaneously monitoring said transactions as they occur over said peripheral bus, said host bridge including register space for temporarily storing the identification of a master peripheral device initiating a transaction and said data being transmitted over said peripheral bus between said master peripheral device and said slave peripheral device during the transaction; and logic for saving said data and identification information in said host bridge register space and generating an interrupt routine over said system bus to said CPU, in response to detection of a parity error over said peripheral bus, wherein said CPU gains access to said peripheral bus in response to said interrupt routine and alternatively (a) reads said register space in said host bridge and attempts recovery operations over said peripheral bus if said status bit is set or (b) relinquishes control of said peripheral bus if said status bit is not set, indicating that a re-initiated transaction has been successfully transacted by said master peripheral device without an occurrence of a parity error.

Claim 3

The system of claim 1, wherein said peripheral bus conforms to Peripheral Component Interconnect (PCI) architecture.

Claim 4

The system of claim 2, wherein said parity errors are detected by monitoring with said host bridge an error status line on said peripheral bus which is activated by said master peripheral device, and wherein said logic for saving said data and said identification information includes logic for inhibiting said register space from being updated in response to activation of said error status line.

Claim 5

The system of claim 2, wherein said register space has additionally stored therein control and address information.

Claim 6

The system of claim 2, wherein said peripheral bus and said system bus have data widths of at least 32 bits.

Claim 7

A parity error detection and recovery mechanism for use in a computer system which comprises (i) a system bus having connected thereto a central processing unit (CPU); (ii) a peripheral bus having connected thereto a master peripheral device which initiates transactions over said peripheral bus in which data is transferred between said master peripheral device and a slave peripheral device connected to said peripheral bus, said master peripheral device able to detect parity errors occurring during said transactions and re-initiate a transaction if a parity error is detected; and (iii) a host bridge connecting said system bus to a peripheral bus for simultaneously monitoring said transactions as they occur over said peripheral bus; said parity error detection and recovery mechanism comprising: a status register which is set by said master peripheral device upon detection of a parity error occurring during a transaction, and which is reset by said master peripheral device if a re-initiated transaction is successfully transacted without an occurrence of a parity error; register space in said host bridge for temporarily storing the identification of a master peripheral device initiating a transaction and said data being transmitted over said peripheral bus between said master peripheral device and said slave peripheral device during the transaction; and logic for saving said data and identification information in said host bridge register space and generating an interrupt routine over said system bus to said CPU, in response to detection of a parity error over said peripheral bus, wherein said CPU gains access to said peripheral bus in response to said interrupt routine and alternatively (a) reads said register space in said host bridge and attempts recovery operations over said peripheral bus if said status bit is set or (b) relinquishes control of said peripheral bus if said status bit is not set, indicating that a re-initiated transaction has been successfully transacted by said master peripheral device without an occurrence of a parity error.

Claim 8

A parity error detection and recovery mechanism for use in a computer system which comprises (i) a system bus having connected thereto a central processing unit (CPU); (ii) a peripheral bus having connected thereto a master peripheral device which initiates transactions over said peripheral bus in which data is transferred between said master peripheral device and a slave peripheral device connected to said peripheral bus, said master peripheral device able to detect parity errors occurring during said transactions and re-initiate a transaction if a parity error is detected; and (iii) a host bridge connecting said system bus to a peripheral bus for simultaneously monitoring said transactions as they occur over said peripheral bus; said parity error detection and recovery mechanism comprising: a status register which is set by said master peripheral device upon detection of a parity error occurring during a transaction, and which is reset by said master peripheral device if a re-initiated transaction is successfully transacted without an occurrence of a parity error; register space in said host bridge for temporarily storing the identification of a master peripheral device initiating a transaction and said data being transmitted over said peripheral bus between said master peripheral device and said slave peripheral device during the transaction; and logic for saving said data and identification information in said host bridge register space and generating an interrupt routine over said system bus to said CPU, in response to detection of a parity error over said peripheral bus, wherein said CPU gains access to said peripheral bus in response to said interrupt routine and alternatively (a) reads said register space in said host bridge and attempts recovery operations over said peripheral bus if said status bit is set or (b) relinquishes control of said peripheral bus if said status bit is not set, indicating that a re-initiated transaction has been successfully transacted by said master peripheral device without an occurrence of a parity error.

Claim 9

The mechanism of claim 6, wherein said peripheral bus conforms to Peripheral Component Interconnect (PCI) architecture.

Claim 10

The mechanism of claim 7, wherein said parity errors are detected by monitoring with said host bridge an error status line on said peripheral bus which is activated by said master peripheral device, and wherein said logic for saving said data and said identification information includes logic for inhibiting said register space from being updated in response to activation of said error status line.

Claim 11

The mechanism of claim 7, wherein said register space has additionally stored therein control and address information.

Claim 12

The mechanism of claim 7, wherein said peripheral bus and said system bus have data widths of at least 32 bits.

Claim 15

The method of claim 11, wherein said peripheral bus conforms to Peripheral Component Interconnect (PCI) architecture.

Claim 16

The method of claim 12, wherein said step of detecting a parity error is accomplished by monitoring with said host bridge an error status line on said peripheral bus which is activated by said master peripheral device, and wherein the step of storing in register space includes the step of inhibiting said register space from being updated in response to activation of said error status line.

Claim 17

The method of claim 12, wherein said register space has additionally stored therein control and address information.

Claim 18

The method of claim 12, wherein said peripheral bus and said system bus have data widths of at least 32 bits.