EPROM with trench in thick field oxide

Claim 1

An erasable-programmable read only memory (EPROM) comprising: a semiconductor substrate; a field insulating layer defining a device formation region of said semiconductor substrate, wherein the device formation region includes a source region and a drain region; a gate insulating layer formed on said device formation region; a floating gate formed on said gate insulating layer and said field insulating layer, wherein the floating gate does not substantially extend above the source region and the drain region; a trench insulating layer extending into said semiconductor substrate at a center portion of said field insulating layer, one of side walls of said trench insulating layer being partially self-aligned with an end face of said floating gate; a first interlaminar insulating layer covering said floating gate; a control gate formed on said first interlaminar insulating layer and located above said floating gate; a second interlaminar insulating layer formed over said control gate; and a bit line formed on said second interlaminar insulating layer and traversing said floating gate and control gate, wherein the control gate is a word line arranged in a perpendicular direction to the bit line, and to a carrier flow direction between the source region and the drain region.