Patent US5498890A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5498890A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having a multi-layered dielectric structure and manufacturing method thereof

Assignee: Samsung Electronics Co Ltd
•
Filing: 1992-07-06
•
Granted: 1996-03-12
•
Expires: 2012-07-06
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor device and a manufacturing method thereof are disclpsed, the semiconductor device comprising: a first conductive layer; an oxide layer formed upon the first conductive layer; a nitride layer composed of multiple sublayers formed upon the oxide layer; another oxide layer formed upon the nitride layer in the form of multiple sublayers; and a second conductive layer formed upon the structure obtained through the preceding steps. Due to the unique feature of the nitride layer composed of multiple sublayers, the electrical characteristics of the semiconductor device according to the present invention is improved, and the nitride layer according to the present invention is widely applicable to semiconductor devices.

Inventors

  • 👤 Sungtae Kim
  • 👤 Soohan Choi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 06:08
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/60; H10P14/66; H10P14/662; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B41/00; H10B41/30; H10B69/00; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/68; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10P14/32; H10P14/3202; H10P14/3214; H10P14/3216; H10P14/3224; H10P14/3226; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/65; H10P14/6516; H10P14/6518; H10P14/6519; H10P14/6522; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 76 words
A semiconductor device comprising a first electrical conductive layer formed on a semiconductor substrate; a first silicon oxide layer formed on said first electrical conductive layer; at least two silicon nitride sublayers formed on said first silicon oxide layer; a second silicon oxide layer formed on said silicon nitride sublayers; and a second electrical conductive layer formed on said second silicon oxide layer, wherein an ultra-thin silicon oxide layer is disposed between said silicon nitride sublayers.
Claim 2
Dependent Claim 76 words
A semiconductor device comprising a first electrical conductive layer formed on a semiconductor substrate; a first silicon oxide layer formed on said first electrical conductive layer; at least two silicon nitride sublayers formed on said first silicon oxide layer; a second silicon oxide layer formed on said silicon nitride sublayers; and a second electrical conductive layer formed on said second silicon oxide layer, wherein an ultra-thin silicon oxide layer is disposed between said silicon nitride sublayers.
Claim 3
Dependent Claim 21 words
The semiconductor device as claimed in claim 1, wherein said ultra-thin silicon oxide layer has a thickness of less than 10Å.
Claim 4
Dependent Claim 22 words
The semiconductor device as claimed in claim 1, wherein said at least two silicon nitride sublayers have a combined thickness of 50Å-200Å.

References Cited (Backward Citations)

JPS61145854A Cited
US5051794A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-03-12 1999-09-11 2000-03-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-03-12 2003-09-11 2004-03-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-03-12 2007-09-11 2008-03-12 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag