US5497458A
Expired / Lapsed
US
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Cache testability circuit for embedded diagnostics
Assignee: Dell USA LP
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Filing: 1993-07-06
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Granted: 1996-03-05
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Expires: 2013-07-06
Abstract
Abstract A memory write disable circuit which disables write operations to main memory during cache diagnostics and thus provides a generic means for testing cache memory systems. Disabling write operations to main memory allows the diagnostics to easily distinguish between cache hits and cache misses during diagnostics. The disable circuit operates by disabling the output enable for the main memory write signal. This disables writes to main memory in a manner external to the memory controller and thus allows tags to be loaded from a cacheable space in main memory. This enables the testing of cache memory systems in computer systems using integrated cache and memory controllers which prevent read hits to memory addresses whose cacheability has been disabled. This also provides a testability function that is hardware independent and thus can be used regardless of the configuration or processor used in the computer system.
Inventors
- 👤 Richard Finch
- 👤 Eric Schieve
- 👤 Joseph Vivio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:02
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
149 words
An apparatus for disabling writes to, but not reads from, main memory in a computer system during cache memory diagnostics, wherein the computer system comprises a CPU, cache memory coupled to the CPU, a cache controller coupled to the CPU and the cache memory, main memory, and a memory controller coupled to the main memory, the CPU, and the cache controller, the apparatus comprising: a buffer coupled between the memory controller and the main memory which receives a write signal from the memory controller and provides said write signal to the main memory; and a signal source coupled to said buffer which asserts a disable signal to said buffer during cache memory diagnostics, wherein said disable signal prevents assertion of said write signal to the main memory during said cache memory diagnostics but does not prevent assertion of read signals to the main memory during said cache memory diagnostics.
Claim 2
Independent Claim
149 words
An apparatus for disabling writes to, but not reads from, main memory in a computer system during cache memory diagnostics, wherein the computer system comprises a CPU, cache memory coupled to the CPU, a cache controller coupled to the CPU and the cache memory, main memory, and a memory controller coupled to the main memory, the CPU, and the cache controller, the apparatus comprising: a buffer coupled between the memory controller and the main memory which receives a write signal from the memory controller and provides said write signal to the main memory; and a signal source coupled to said buffer which asserts a disable signal to said buffer during cache memory diagnostics, wherein said disable signal prevents assertion of said write signal to the main memory during said cache memory diagnostics but does not prevent assertion of read signals to the main memory during said cache memory diagnostics.
Claim 3
Dependent Claim
83 words
The apparatus of claim 1, wherein said memory comprises a plurality of memory locations forming an address space and portions of said address space can be designated cacheable or noncacheable by the memory controller; wherein if a portion of said memory locations corresponding to a first address space is disabled, the memory controller designates said first address space to be non-cacheable; and wherein the memory controller does not allow hits to the cache memory involving memory addresses corresponding to a non-cacheable address space.
Claim 4
Dependent Claim
17 words
The apparatus of claim 2, wherein the memory controller and the cache controller are the Intel 82424.
Claim 5
Dependent Claim
34 words
The apparatus of claim 1, wherein said buffer includes an output enable input; and wherein said disable signal is asserted to said output enable input of said buffer to disable outputs from said buffer.
Claim 6
Dependent Claim
12 words
The apparatus of claim 1, wherein said signal source comprises a port.
Claim 7
Dependent Claim
132 words
A computer system which performs cache memory diagnostics, comprising: a CPU; cache memory coupled to the CPU; a cache controller coupled to the CPU and the cache memory; main memory; a memory controller coupled to the main memory, the CPU, and the cache controller; a buffer coupled between the memory controller and the main memory which receives a write signal from the memory controller and provides said write signal to the main memory; and a signal source coupled to said buffer and the CPU which asserts a disable signal to said buffer during cache memory diagnostics, wherein said disable signal prevents assertion of said write signal to the main memory during said cache memory diagnostics but does not prevent assertion of read signals to the main memory during said cache memory diagnostics.
Claim 8
Dependent Claim
132 words
A computer system which performs cache memory diagnostics, comprising: a CPU; cache memory coupled to the CPU; a cache controller coupled to the CPU and the cache memory; main memory; a memory controller coupled to the main memory, the CPU, and the cache controller; a buffer coupled between the memory controller and the main memory which receives a write signal from the memory controller and provides said write signal to the main memory; and a signal source coupled to said buffer and the CPU which asserts a disable signal to said buffer during cache memory diagnostics, wherein said disable signal prevents assertion of said write signal to the main memory during said cache memory diagnostics but does not prevent assertion of read signals to the main memory during said cache memory diagnostics.
Claim 9
Dependent Claim
81 words
The computer system of claim 6, wherein said main memory comprises a plurality of memory locations forming an address space and portions of said address space can be designated cacheable or noncacheable; wherein if a portion of said memory locations corresponding to a first address space are disabled, the memory controller designates said first address space to be non-cacheable; and wherein the memory controller does not allow hits to the cache memory involving memory addresses corresponding to a non-cacheable address space.
Claim 10
Dependent Claim
18 words
The computer system of claim 7, wherein the memory controller and the cache controller are the Intel 82424.
Claim 11
Dependent Claim
35 words
The computer system of claim 6, wherein said buffer includes an output enable input; and wherein said disable signal is asserted to said output enable input of said buffer to disable outputs from said buffer.
Claim 12
Dependent Claim
12 words
The computer system of claim 6, wherein said circuit comprises a port.
Claim 13
Independent Claim
137 words
A method for performing cache memory diagnostics in a computer system comprising a CPU, a cache system coupled to the CPU including cache memory and a cache controller, main memory, and a memory controller coupled to the main memory, the CPU, and the cache controller, wherein the memory controller does not allow hits to the cache memory involving memory addresses corresponding to a non-cacheable address space, and a buffer coupled between the memory controller and the main memory which receives a write signal from the memory controller and provides said write signal to the main memory, the method comprising: disabling write operations to, but not read operations from, the main memory by disabling operation of said buffer; loading tag addresses into the cache system; and testing the cache memory after performing said steps of disabling and loading.
Claim 14
Independent Claim
137 words
A method for performing cache memory diagnostics in a computer system comprising a CPU, a cache system coupled to the CPU including cache memory and a cache controller, main memory, and a memory controller coupled to the main memory, the CPU, and the cache controller, wherein the memory controller does not allow hits to the cache memory involving memory addresses corresponding to a non-cacheable address space, and a buffer coupled between the memory controller and the main memory which receives a write signal from the memory controller and provides said write signal to the main memory, the method comprising: disabling write operations to, but not read operations from, the main memory by disabling operation of said buffer; loading tag addresses into the cache system; and testing the cache memory after performing said steps of disabling and loading.
Claim 15
Dependent Claim
27 words
The method of claim 11, further comprising: sizing the cache memory after performing said steps of disabling and loading and before said step of cache memory testing.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-05 | 1999-09-04 | 2000-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-05 | 2003-09-04 | 2004-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-05 | 2007-09-04 | 2008-03-05 | $7700.00 | Window Closed / Lapsed |