US5497337A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for designing high-Q inductors in silicon technology without expensive metalization
Assignee: International Business Machines Corp
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Filing: 1994-10-21
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Granted: 1996-03-05
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Expires: 2014-10-21
Abstract
Abstract A method of designing a high Q inductor for implementation in multiple metalization levels in conventional integrated circuit technology uses a software assisted iterative technique to achieve a design Q factor. The inductor turns utilize the multiple metalization levels to reduce inductor resistance.
Inventors
- 👤 Saila Ponnapalli
- 👤 Mehmet Soyuer
- 👤 John F. Ewen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:51
CPC Classifications
H; H10; H10D; H10D84/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
156 words
A computer implemented method for designing a high-Q spiral inductor as part of an integrated circuit, the spiral inductor being implemented in a plurality of wiring levels in the integrated circuit, the comprising the steps of: (a) graphically modeling a geometrical structure of the plurality of wiring levels and via holes which connect said wiring levels to implement a plurality of spiral turns of the inductor; (b) computing an inductance, resistance and parasitic capacitance for the modeled geometrical structure using a method of moments algorithm; (c) computing a Q factor based on said computed inductance, resistance, and parasitic capacitance; and (d) determining if the Q factor for the modeled geometric structure is greater than a predetermined value; (e) redesigning a number of layers or width of lines of the geometric structure if the Q factor is not greater than said predetermined value; and (f) repeating steps (a) through (e) until a sufficiently high Q is obtained.
Claim 2
Dependent Claim
156 words
A computer implemented method for designing a high-Q spiral inductor as part of an integrated circuit, the spiral inductor being implemented in a plurality of wiring levels in the integrated circuit, the comprising the steps of: (a) graphically modeling a geometrical structure of the plurality of wiring levels and via holes which connect said wiring levels to implement a plurality of spiral turns of the inductor; (b) computing an inductance, resistance and parasitic capacitance for the modeled geometrical structure using a method of moments algorithm; (c) computing a Q factor based on said computed inductance, resistance, and parasitic capacitance; and (d) determining if the Q factor for the modeled geometric structure is greater than a predetermined value; (e) redesigning a number of layers or width of lines of the geometric structure if the Q factor is not greater than said predetermined value; and (f) repeating steps (a) through (e) until a sufficiently high Q is obtained.
Claim 3
Dependent Claim
40 words
The method recited in claim 1 wherein said step of graphically modeling is performed using a computer software graphical modeling program which creates a graphical model and a meshed model with triangular elements of a resonator structure including the inductor.
Claim 4
Dependent Claim
46 words
The method recited in claim 2 wherein step (b) is performed using the method of moments algorithm in which the geometry of the resonator structure is meshed into triangles in which a piece wise constant charge distribution and a piece wise linear current distribution is employed.
Claim 5
Dependent Claim
196 words
A computer implemented method of designing a high Q monolithic inductor structure formed using a conventional silicon technology comprising at least first and second metal levels separated from one another by a first insulating layer, said first and second metal levels being formed with identical spiral patterns and connected through via holes in the first insulating layer to implement parallel connected turns of the inductor structure having a low resistance value, said method comprising the steps of: (a) graphically modeling a geometrical structure of the plurality of wiring levels and via holes which connect said wiring levels to implement a plurality of spiral turns of the inductor; (b) computing an inductance, resistance and parasitic capacitance for the modeled geometrical structure using a method of moments algorithm; (c) computing a Q factor based on said computed inductance, resistance, and parasitic capacitance; (d) determining if the Q factor for the modeled geometric structure is greater than a predetermined value; (e) redesigning a number of layers or width of lines of the geometric structure if the Q factor is not greater than said predetermined value; and (f) repeating steps (a) through (e) until a sufficiently high Q is obtained.
Claim 6
Dependent Claim
196 words
A computer implemented method of designing a high Q monolithic inductor structure formed using a conventional silicon technology comprising at least first and second metal levels separated from one another by a first insulating layer, said first and second metal levels being formed with identical spiral patterns and connected through via holes in the first insulating layer to implement parallel connected turns of the inductor structure having a low resistance value, said method comprising the steps of: (a) graphically modeling a geometrical structure of the plurality of wiring levels and via holes which connect said wiring levels to implement a plurality of spiral turns of the inductor; (b) computing an inductance, resistance and parasitic capacitance for the modeled geometrical structure using a method of moments algorithm; (c) computing a Q factor based on said computed inductance, resistance, and parasitic capacitance; (d) determining if the Q factor for the modeled geometric structure is greater than a predetermined value; (e) redesigning a number of layers or width of lines of the geometric structure if the Q factor is not greater than said predetermined value; and (f) repeating steps (a) through (e) until a sufficiently high Q is obtained.
Claim 7
Dependent Claim
81 words
The method recited in claim 4 wherein said step of graphically modeling is performed using a computer software graphical modeling program which creates a graphical model and a meshed model with triangular elements of a resonator structure including the inductor and wherein step (b) is performed using the method of moments algorithm in which the geometry of the resonator structure is meshed into triangles in which a piece wise constant charge distribution and a piece wise linear current distribution is assumed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-05 | 1999-09-04 | 2000-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-05 | 2003-09-04 | 2004-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-05 | 2007-09-04 | 2008-03-05 | $7700.00 | Window Closed / Lapsed |