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US5497079A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor testing apparatus, semiconductor testing circuit chip, and probe card

Assignee: Panasonic Holdings Corp
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Filing: 1993-08-31
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Granted: 1996-03-05
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Expires: 2013-08-31
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Abstract

Abstract The present invention comprises a plurality of semiconductor testing circuit chips 2 having an exclusive function of testing a plurality of one item of semiconductor integrated-circuit chips 1, a computer 3 for controlling the semiconductor testing circuit chips 2 and for collecting the test results, and a motherboard 4 on which the plurality of chips 1 to be tested and the plurality of testing circuit chips 2 are mounted so that the chips 1 to be tested are connected to the testing circuit chips 2. Since the major testing functions are incorporated into the testing circuit chips 2, the computer 3 for collecting the test results can sufficiently be composed of a low-price computer, so that it is possible to greatly lower the price of the semiconductor testing apparatus. By increasing the number of the testing circuit chips 2, it is possible to greatly increase the number of chips which can be tested simultaneously. Consequently, there can be provided a semiconductor testing apparatus which realizes the reduction in price and the increase in number of the semiconductor integrated circuits tested simultaneously, thereby significantly reducing the cost of testing the semiconductor integrated circuits.

Inventors

  • 👤 Toshio Yamada
  • 👤 Atsushi Fujiwara
  • 👤 Michihiro Inoue
  • 👤 Kazuhiro Matsuyama

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 10:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31935; G01R31/2851; G01R31/2884; G11; G11C; G11C29/00; G11C29/56

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 85 words
A semiconductor testing apparatus for testing semiconductor integrated-circuit chips, comprising: a plurality of semiconductor testing circuit chips, each of which functions to test a single semiconductor integrated-circuit chip; a computer for controlling said semiconductor testing circuit chips and for collecting the results of the testing of said semiconductor integrated-circuit chips, said results generated by each of said plurality of semiconductor testing circuit chips; and means for connecting each of said plurality of semiconductor testing circuit chips to a single semiconductor integrated-circuit chip to be tested.
Claim 2
Dependent Claim 85 words
A semiconductor testing apparatus for testing semiconductor integrated-circuit chips, comprising: a plurality of semiconductor testing circuit chips, each of which functions to test a single semiconductor integrated-circuit chip; a computer for controlling said semiconductor testing circuit chips and for collecting the results of the testing of said semiconductor integrated-circuit chips, said results generated by each of said plurality of semiconductor testing circuit chips; and means for connecting each of said plurality of semiconductor testing circuit chips to a single semiconductor integrated-circuit chip to be tested.
Claim 3
Dependent Claim 23 words
A semiconductor testing apparatus according to claim 1, wherein the connecting means is a motherboard formed in the shape of a flat board.
Claim 4
Dependent Claim 33 words
A semiconductor testing apparatus according to claim 1, wherein the number of the plurality of semiconductor integrated-circuit chips to be tested is the same as the number of the semiconductor testing circuit chips.
Claim 5
Dependent Claim 41 words
A semiconductor testing apparatus according to claim 2, wherein the plurality of semiconductor integrated-circuit chips to be tested are disposed on one surface of the motherboard and the semiconductor testing circuit chips are formed on the other surface of the motherboard.

References Cited (Backward Citations)

US5132613A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-03-05 1999-09-04 2000-03-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-03-05 2003-09-04 2004-03-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-03-05 2007-09-04 2008-03-05 $7700.00 Window Closed / Lapsed

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