Pre-charged exclusionary wired-connected programmed redundant select

Claim 2

A redundant decode structure of a high speed clocked memory device, comprising: a plurality of programmable elements of an exclusionary wired-connection redundant select circuit; a plurality of address input signals which are connected to and control the plurality of programmable elements; a first controlling clock input signal, provided to the plurality of programmable elements, characterized as having an active portion and an inactive portion; an enable circuit connected to the plurality of programmable elements which enables or disables the exclusionary wired-connection redundant select circuit; means, connected to the plurality of programmable elements, for programming an address of a defective element of the high speed clocked memory device by disconnecting all the programmable elements of the plurality of programmable elements of the exclusionary wired-connection redundant select circuit which are not representative of the address of the defective element from their corresponding address input signals of the plurality of address input signals, wherein, after programming the address of the defective element, during the inactive portion of the first controlling clock the address of the defective element becomes valid; and an output signal of the exclusionary wired-connection redundant select circuit connected to the means for programming an address of a defective element of the high speed clocked memory device.

Claim 3

The structure of claim 1, wherein the plurality of programmable elements of the exclusionary wired-connection redundant select circuit are laser fuse links.

Claim 4

The structure of claim 1, wherein the enable circuit enables the exclusionary wired-connection redundant select circuit upon programming of a programmable element of the enable circuit.

Claim 5

The structure of claim 3, wherein the programmable element of the enable circuit is a laser fuse link and programming the laser fuse link is accomplished by disconnecting the laser fuse link.

Claim 6

The structure of claim 1, wherein the exclusionary wired-connection redundant select circuit is pre-charged to a selected state during the inactive portion of the first controlling clock input signal.

Claim 7

The structure of claim 5, wherein the pre-charging of the exclusionary wired-connection redundant select circuit is terminated during an active portion of a second controlling clock input signal, and after termination of the pre-charging, the output signal resolves to a logic state that is determined by the address input signals.

Claim 8

The structure of claim 6, wherein the plurality of address input signals are stable when the pre-charging of the exclusionary wired-connection redundant select circuit is terminated.

Claim 9

The structure of claim 1, wherein during pre-charging of the exclusionary wired-connection redundant select circuit to a level of a first supply voltage, the programmable elements are disconnected from a second supply voltage and the output signal is pre-charged to the level of the first supply voltage.

Claim 10

The structure of claim 1, wherein the exclusionary wired-connection redundant select circuit is an exclusionary wired-connection redundant row select circuit and the defective element is a defective row.

Claim 11

The structure of claim 1, wherein the exclusionary wired-connection redundant select circuit further comprises: a plurality of transistor elements of a first polarity, wherein a first source/drain of each of the transistor elements is connected to a first supply voltage via a first pull-up/pull-down transistor of the first polarity, a second source/drain of each of the transistor elements is connected to a first terminal of each of the plurality of programmable elements, a gate of each of the transistor elements is controlled by a different address input signal of the plurality of address input signals; wherein a gate of the first pull-up/pull-down transistor is controlled by a second controlling clock input signal; a second terminal of each of the plurality of programmable elements is connected to a second supply voltage via a second pull-up/pull-down transistor of a second polarity, wherein a gate of the second pull-up/pull-down transistor is controlled by the first controlling clock input signal.

Claim 12

The structure of claim 1, wherein the exclusionary wired-connection redundant select circuit further comprises: a plurality of transistor elements of a first polarity, wherein a first source/drain of each of the transistor elements is connected to a first supply voltage via a first pull-up/pull-down transistor of the first polarity, a second source/drain of each of the transistor elements is connected to a first terminal of each of the plurality of programmable elements, a gate of each of the transistor elements is controlled by a different address input signal of the plurality of address input signals; wherein a gate of the first pull-up/pull-down transistor is controlled by the first controlling clock input signal; a second terminal of each of the plurality of programmable elements is connected to a second supply voltage via a second pull-up/pull-down transistor of a second polarity, wherein a gate of the second pull-up/pull-down transistor is controlled by the first controlling clock input signal.

Claim 13

The structure of claim 1, wherein the exclusionary wired-connection redundant select circuit is an exclusionary wired-AND redundant select circuit.

Claim 14

A redundant decode structure of a high speed clocked memory device, comprising: a plurality of programmable elements of an exclusionary wired-connection redundant select circuit; a plurality of address input signals which are connected to and control the plurality of programmable elements; a first controlling clock input signal, provided to the plurality of programmable elements, characterized as having an active portion and an inactive portion; an enable circuit connected to the plurality of programmable elements which enables or disables the exclusionary wired-connection redundant select circuit; means, connected to the plurality of programmable elements, for programming an address of a defective element of the high speed clocked memory device by disconnecting all the programmable elements of the plurality of programmable elements of the exclusionary wired-connection redundant select circuit which are not representative of the address of the defective element from their corresponding address input signals of the plurality of address input signals, wherein, after programming the address of the defective element, during the inactive portion of the first controlling clock the address of the defective element becomes valid; an output signal of the exclusionary wired-connection redundant select circuit connected to the means for programming an address of a defective element of the high speed clocked memory device; and means for storing the output signal of the exclusionary wired-connection redundant select circuit.

Claim 15

A redundant decode structure of a high speed clocked memory device, comprising: a plurality of programmable elements of an exclusionary wired-connection redundant select circuit; a plurality of address input signals which are connected to and control the plurality of programmable elements; a first controlling clock input signal, provided to the plurality of programmable elements, characterized as having an active portion and an inactive portion; an enable circuit connected to the plurality of programmable elements which enables or disables the exclusionary wired-connection redundant select circuit; means, connected to the plurality of programmable elements, for programming an address of a defective element of the high speed clocked memory device by disconnecting all the programmable elements of the plurality of programmable elements of the exclusionary wired-connection redundant select circuit which are not representative of the address of the defective element from their corresponding address input signals of the plurality of address input signals, wherein, after programming the address of the defective element, during the inactive portion of the first controlling clock the address of the defective element becomes valid; an output signal of the exclusionary wired-connection redundant select circuit connected to the means for programming an address of a defective element of the high speed clocked memory device; and means for storing the output signal of the exclusionary wired-connection redundant select circuit.

Claim 16

The structure of claim 13, wherein the plurality of programmable elements of the exclusionary wired-connection redundant select circuit are laser fuse links.

Claim 17

The structure of claim 13, wherein the enable circuit enables the exclusionary wired-connection redundant select circuit upon programming of a programmable element of the enable circuit.

Claim 18

The structure of claim 15, wherein the programmable element of the enable circuit is a laser fuse link and programming the laser fuse link is accomplished by disconnecting the laser fuse link.

Claim 19

The structure of claim 13, wherein the exclusionary wired-connection redundant select circuit is pre-charged to a selected state during the inactive portion of the first controlling clock input signal.

Claim 20

The structure of claim 17, wherein the pre-charging of the exclusionary wired-connection redundant select circuit is terminated during an active portion of a second controlling clock input signal, and after termination of the pre-charging, the output signal resolves to a logic state that is determined by the address input signals.

Claim 21

The structure of claim 18, wherein the address input signals are stable when the pre-charging of the exclusionary wired-connection redundant select circuit is terminated.

Claim 22

The structure of claim 18, wherein the resolved logic state of the output signal controls the output of a latch during the active state of the first controlling clock input signal.

Claim 23

The structure of claim 20, wherein during the inactive portion of the first controlling clock input signal, the latch stores the output signal from the active portion of the first controlling clock input signal which preceded the inactive portion.

Claim 24

The structure of claim 13, wherein during pre-charging of the exclusionary wired-connection redundant select circuit to a level of a first supply voltage, the programmable elements are disconnected from a second supply voltage and the output signal is pre-charged to the level of the first supply voltage.

Claim 25

The structure of claim 13, wherein the exclusionary wired-connection redundant select circuit is an exclusionary wired-connection redundant row select circuit and the defective element is a defective row.

Claim 26

The structure of claim 13, wherein the exclusionary wired-connection redundant select circuit further comprises: a plurality of transistor elements of a first: polarity, wherein a first source/drain of each of the transistor elements is connected to a first supply voltage via a first pull-up/pull-down transistor of the first polarity, a second source/drain of each of the transistor elements is connected to a first terminal of each of the plurality of programmable elements, a gate of each of the transistor elements is controlled by a different address input signal of the plurality of address input signals; wherein a gate of the first pull-up/pull-down transistor is controlled by a second controlling clock input signal; a second terminal of each of the plurality of programmable elements is connected to a second supply voltage via a second pull-up/pull-down transistor of a second polarity, wherein a gate of the second pull-up/pull-down transistor is controlled by the first controlling clock input signal.

Claim 27

The structure of claim 13, wherein the exclusionary wired-connection redundant select circuit further comprises: a plurality of transistor elements of a first polarity, wherein a first source/drain of each of the transistor elements is connected to a first supply voltage via a first pull-up/pull-down transistor of the first polarity, a second source/drain of each of the transistor elements is connected to a first terminal of each of the plurality of programmable elements, a gate of each of the transistor elements is controlled by a different address input signal of the plurality of address input signals; wherein a gate of the first pull-up/pull-down transistor is controlled by the first controlling clock input signal; a second terminal of each of the plurality of programmable elements is connected to a second supply voltage via a second pull-up/pull-down transistor of a second polarity, wherein a gate of the second pull-up/pull-down transistor is controlled by the first controlling clock input signal.

Claim 30

The method of claim 26, wherein the exclusionary wired-connection redundant select circuit is enabled upon programming a programmable element of the enable circuit.

Claim 31

The method of claim 27, wherein the programmable element of the enable circuit is a laser fuse link and programming the laser fuse link is accomplished by disconnecting the laser fuse link.

Claim 32

The method of claim 26, wherein the plurality of programmable elements of the exclusionary wired-connection redundant select circuit are laser fuse links.

Claim 33

The method of claim 26, wherein the exclusionary wired-connection redundant select circuit is pre-charged to a selected state during the inactive portion of the first controlling clock input signal.

Claim 34

The method of claim 30, wherein the pre-charging of the exclusionary wired-connection redundant select circuit is terminated during an active portion of a second controlling clock input signal, and after termination of the pre-charging, an output signal of the exclusionary wired-connection redundant select circuit resolves to a logic state that is determined by the address input signals.

Claim 35

The method of claim 31, wherein the address input signals are stable when the pre-charging of the exclusionary wired-connection redundant select circuit is terminated.

Claim 36

The method of claim 26, wherein during pre-charging of the exclusionary wired-connection redundant select circuit to a level of a first supply voltage, the programmable elements are disconnected from a second supply voltage and an output signal of the exclusionary wired-connection redundant select circuit is pre-charged to the level of the first supply voltage.

Claim 37

The method of claim 26, wherein the exclusionary wired-connection redundant select circuit is an exclusionary wired-connection redundant row select circuit and the defective element is a defective row.

Claim 38

The method of claim 26, after the step of programming the address of the defective element and before the step of enabling the redundant element, comprising the further step of: storing an output signal of the exclusionary wired-connection redundant select circuit.

Claim 39

The method of claim 35, wherein a resolved logic state of the output signal of the exclusionary wired-connection redundant select circuit controls an output signal of a latch during the active state of the first controlling clock input signal.

Claim 40

The method of claim 36, wherein during the inactive portion of the first controlling clock input signal, the latch stores the output signal of the exclusionary wired-connection redundant select circuit from the active portion of the first controlling clock input signal which preceded the inactive portion.

Claim 41

The method of claim 26, wherein the exclusionary wired-connection redundant select circuit is an exclusionary wired-AND redundant select circuit.