Patent US5495205A successfully refreshed from Google Patents.
US5495205A
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Digital controlled oscillator and method thereof
Assignee: Motorola Solutions Inc
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Filing: 1995-01-06
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Granted: 1996-02-27
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Expires: 2015-01-06
Abstract
Abstract A digital controlled oscillator (14) generates an oscillator clock that is phase locked to a reference clock. A control circuit (12) generates a reset signal from the reference clock that sets the edges of the oscillator signal in line with an edge of the reference clock. The reset signal must have correct timing and duration. A course tune detector (16, 18) monitors the oscillator clock and generates course tune control signals (CT) that adjust the reset signal pulse width and the oscillator signal frequency by adding and removing capacitors from the inverters in the control circuit and digital controlled oscillator. A phase comparator (22) compares the reference clock and the oscillator clock. A fine tune detector (20) monitors the phase comparison and generates fine tune control signals (FT) that make fine adjustments to the pulse width of the reset signal and the frequency of the oscillator signal.
Inventors
- 👤 Lanny L. Parker
- 👤 Ahmad H. Atriss
- 👤 Benjamin C. Peterson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:10
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L2207/00; H03L2207/06
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
49 words
A digital controlled oscillator, comprising: an oscillating circuit operating in response to a reset signal for generating an oscillator clock signal; and a control circuit operating in response to a reference clock signal for generating said reset signal that aligns said oscillator clock signal to said reference clock signal.
Claim 2
Dependent Claim
49 words
A digital controlled oscillator, comprising: an oscillating circuit operating in response to a reset signal for generating an oscillator clock signal; and a control circuit operating in response to a reference clock signal for generating said reset signal that aligns said oscillator clock signal to said reference clock signal.
Claim 3
Dependent Claim
54 words
The digital controlled oscillator of claim 1 wherein said oscillating circuit includes: a plurality of serially coupled first inverters where an input of a first one is coupled to an output of a last one for providing said oscillator clock signal; and a plurality of first capacitors coupled to outputs of said first inverters.
Claim 4
Dependent Claim
40 words
The digital controlled oscillator of claim 2 wherein said oscillating circuit further generates a load control signal at a first edge of said oscillator clock signal and a transfer control signal at a second edge of said oscillator clock signal.
Claim 5
Dependent Claim
129 words
The digital controlled oscillator of claim 3 wherein said control circuit includes: a course tune frequency detect circuit operating in response to said load control signal and said transfer control signal for generating an overflow control signal that changes state upon receiving a predetermined number of said load control signals and transfer control signals within a predetermined period; a course tune detector operating in response to said state of said overflow control signal for generating a course tune control signal that connects and disconnects said plurality of first capacitors from said outputs of said first inverters to perform frequency adjustments on said oscillator clock signal; and a phase correction circuit operating in response to said course tune control signal to perform pulse width adjustments on said reset control signal.
Claim 6
Dependent Claim
76 words
The digital controlled oscillator of claim 4 wherein said phase correction circuit includes: a plurality of serially coupled second inverters having an input coupled for receiving said reference clock signal and having an output for providing said reset signal; and a plurality of second capacitors that are coupled to and disconnected from said outputs of said second inverters in response to said course tune control signal to perform pulse width adjustments on said reset control signal.
Claim 7
Dependent Claim
152 words
The digital controlled oscillator of claim 5 wherein said control circuit further includes: a phase detector responsive to said reference clock signal and said oscillator clock signal for generating a compare control signal having a first logic state when said oscillator clock signal leads said reference clock signal and a second logic state when said oscillator clock signal lags said reference clock signal; and a fine tune detector operating in response to said first and second logic states of said compare control signal for generating a fine tune control signal that connects and disconnects a plurality of third capacitors from said outputs of said first inverters to perform frequency adjustments on said oscillator clock signal, said fine tune control signal further controlling said phase correction circuit to connect and disconnect a plurality of fourth capacitors from said outputs of said second inverters to perform pulse width adjustments on said reset control signal.
Claim 8
Independent Claim
45 words
A method of digitally controlling an oscillator, comprising the steps of: generating an oscillator clock signal in response to a reset signal; and generating said reset signal in response to a reference clock signal that aligns said oscillator clock signal to said reference clock signal.
Claim 9
Independent Claim
45 words
A method of digitally controlling an oscillator, comprising the steps of: generating an oscillator clock signal in response to a reset signal; and generating said reset signal in response to a reference clock signal that aligns said oscillator clock signal to said reference clock signal.
Claim 10
Dependent Claim
38 words
The method of claim 7 further including the step of generating a load control signal at a first edge of said oscillator clock signal and a transfer control signal at a second edge of said oscillator clock signal.
Claim 11
Dependent Claim
48 words
The method of claim 8 further including the step of generating an overflow control signal in response to said load control signal and said transfer control signal that changes state upon receiving a predetermined number of said load control signals and transfer control signals within a predetermined period.
Claim 12
Dependent Claim
51 words
The method of claim 9 further including the step of generating a course tune control signal in response to said state of said overflow control signal that connects and disconnects said plurality of first capacitors from said outputs of said first inverters to perform frequency adjustments on said oscillator clock signal.
Claim 13
Dependent Claim
27 words
The method of claim 10 further including the step of performing pulse width adjustments on said reset control signal in response to said course tune control signal.
Claim 14
Dependent Claim
60 words
The method of claim 11 further including the step of generating a compare control signal in response to said reference clock signal and said oscillator clock signal, said compare signal having a first logic state when said oscillator clock signal leads said reference clock signal and a second logic state when said oscillator clock signal lags said reference clock signal.
Claim 15
Dependent Claim
96 words
The method of claim 12 further including the step of generating a fine tune control signal in response to said first and second logic states of said compare control signal, said fine tune control signal connecting and disconnecting a plurality of third capacitors from said outputs of said first inverters to perform frequency adjustments on said oscillator clock signal, said fine tune control signal further controlling said phase correction circuit to connect and disconnect a plurality of fourth capacitors from said outputs of said second inverters to perform pulse width adjustments on said reset control signal.
Claim 16
Dependent Claim
98 words
A digital controlled oscillator, comprising: an oscillating circuit operating in response to a reset signal for generating an oscillator clock signal, said oscillating circuit including, (a) a plurality of serially coupled first inverters where an input of a first one is coupled to an output of a last one for providing said oscillator clock signal, and (b) a first capacitor coupled to an output of one of said first inverters; and a control circuit operating in response to a reference clock signal for generating said reset signal that aligns said oscillator clock signal to said reference clock signal.
Claim 17
Dependent Claim
98 words
A digital controlled oscillator, comprising: an oscillating circuit operating in response to a reset signal for generating an oscillator clock signal, said oscillating circuit including, (a) a plurality of serially coupled first inverters where an input of a first one is coupled to an output of a last one for providing said oscillator clock signal, and (b) a first capacitor coupled to an output of one of said first inverters; and a control circuit operating in response to a reference clock signal for generating said reset signal that aligns said oscillator clock signal to said reference clock signal.
Claim 18
Dependent Claim
40 words
The digital controlled oscillator of claim 14 wherein said oscillating circuit further generates a load control signal at a first edge of said oscillator clock signal and a transfer control signal at a second edge of said oscillator clock signal.
Claim 19
Dependent Claim
129 words
The digital controlled oscillator of claim 15 wherein said control circuit includes: a course tune frequency detect circuit operating in response to said load control signal and said transfer control signal for generating an overflow control signal that changes state upon receiving a predetermined number of said load control signals and transfer control signals within a predetermined period; a course tune detector operating in response to said state of said overflow control signal for generating a course tune control signal that connects and disconnects said plurality of first capacitors from said outputs of said first inverters to perform frequency adjustments on said oscillator clock signal; and a phase correction circuit operating in response to said course tune control signal to perform pulse width adjustments on said reset control signal.
Claim 20
Dependent Claim
39 words
The digital controlled oscillator of claim 16 wherein said phase correction circuit includes a plurality of serially coupled second inverters having an input coupled for receiving said reference clock signal and having an output for providing said reset signal.
Claim 21
Dependent Claim
42 words
The digital controlled oscillator of claim 17 wherein said phase correction circuit further includes a second capacitor that is coupled to and disconnected from an output of one of said second inverters to perform pulse width adjustments on said reset control signal.
Claim 22
Dependent Claim
156 words
The digital controlled oscillator of claim 18 wherein said control circuit further includes: a phase detector responsive to said reference clock signal and said oscillator clock signal for generating a compare control signal having a first logic state when said oscillator clock signal leads said reference clock signal and a second logic state when said oscillator clock signal lags said reference clock signal; and a fine tune detector operating in response to said first and second logic states of said compare control signal for generating a fine tune control signal that connects and disconnects a third capacitor from an output of a second one of said first inverters to perform frequency adjustments on said oscillator clock signal, said fine tune control signal further controlling said phase correction circuit to connect and disconnect a fourth capacitor from an output of a second one of said second inverters to perform pulse width adjustments on said reset control signal.
References Cited (Backward Citations)
US5357217A
Cited
US5302920A
Cited
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