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Patent US5495196A successfully refreshed from Google Patents.
US5495196A
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User controlled reset circuit with fast recovery
Assignee: Xilinx Inc
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Filing: 1994-08-25
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Granted: 1996-02-27
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Expires: 2014-08-25
Abstract
Abstract The present invention allows initializing operations such as loading configuration data and preloading registers to begin before a user has released a reset signal. A circuit is provided which responds to the leading edge of a user's reset signal to generate an internal reset signal which begins the initializing operation. The circuit simultaneously starts a delayed signal which ends the internal reset signal. If the MRX signal is long, the chip becomes ready for operating upon release of the MRX signal, whereas if the MRX signal is short, the chip becomes ready for operating upon completion of any steps necessary for resetting the chip. In either case, after a reset signal is received, the chip becomes ready for operation in a shorter time than with the prior art circuits.
Inventors
- 👤 Daniel J. Rothman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 07:11
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356008
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
66 words
A reset circuit for providing a global reset signal comprising: means for providing a VDD detect signal; means for generating a reset pulse in response to a user-generated master reset signal; means for shaping said reset pulse and outputting a modified reset pulse; and means for receiving said VDD detect signal and said modified reset pulse, providing an OR function, and outputting said global reset signal.
Claim 2
Dependent Claim
66 words
A reset circuit for providing a global reset signal comprising: means for providing a VDD detect signal; means for generating a reset pulse in response to a user-generated master reset signal; means for shaping said reset pulse and outputting a modified reset pulse; and means for receiving said VDD detect signal and said modified reset pulse, providing an OR function, and outputting said global reset signal.
Claim 3
Dependent Claim
74 words
A reset circuit for providing a global reset signal comprising: means for providing a VDD detect signal; means for generating a reset pulse in response to a master reset signal; means for shaping said reset pulse and outputting a modified reset pulse; and a logic device for receiving said VDD detect signal and said modified reset pulse, said logic device outputting said global reset signal, wherein said means for generating includes a seteset latch.
Claim 4
Dependent Claim
74 words
A reset circuit for providing a global reset signal comprising: means for providing a VDD detect signal; means for generating a reset pulse in response to a master reset signal; means for shaping said reset pulse and outputting a modified reset pulse; and a logic device for receiving said VDD detect signal and said modified reset pulse, said logic device outputting said global reset signal, wherein said means for generating includes a seteset latch.
Claim 5
Dependent Claim
19 words
A reset circuit as in claim 2 wherein said means for shaping includes means for delaying said reset pulse.
Claim 6
Dependent Claim
141 words
A reset circuit for providing a global reset signal comprising: means for providing a VDD detect signal; means for generating a reset pulse in response to a master reset signal; means for shaping said reset pulse and outputting a modified reset pulse; and a logic device for receiving said VDD detect signal and said modified reset pulse, said logic device outputting said global reset signal, wherein said means for shaping comprises: a logic gate; a first path for providing said reset pulse to said logic gate; and a second path for providing an inverted, and delayed reset pulse to said logic gate, said second path including a plurality of inverters connected in series and a plurality of capacitors, each capacitor having one terminal connected between two of said plurality of inverters and having another terminal connected to a first voltage source.
Claim 7
Dependent Claim
141 words
A reset circuit for providing a global reset signal comprising: means for providing a VDD detect signal; means for generating a reset pulse in response to a master reset signal; means for shaping said reset pulse and outputting a modified reset pulse; and a logic device for receiving said VDD detect signal and said modified reset pulse, said logic device outputting said global reset signal, wherein said means for shaping comprises: a logic gate; a first path for providing said reset pulse to said logic gate; and a second path for providing an inverted, and delayed reset pulse to said logic gate, said second path including a plurality of inverters connected in series and a plurality of capacitors, each capacitor having one terminal connected between two of said plurality of inverters and having another terminal connected to a first voltage source.
Claim 8
Dependent Claim
68 words
A reset circuit as in claim 1 wherein said means for shaping comprises: a logic gate; a first path for providing said reset pulse to one input terminal of said logic gate; and a second path for delaying and inverting said reset pulse and providing the delayed and inverted reset pulse to another input terminal of said logic gate, wherein said logic gate outputs said modified reset pulse.
Claim 9
Dependent Claim
119 words
A reset circuit for providing a global reset signal comprising: means for providing a VDD detect signal; means for generating a reset pulse in response to a master reset signal; means for shaping said reset pulse and outputting a modified reset pulse; and a logic device for receiving said VDD detect signal and said modified reset pulse, said logic device outputting said global reset signal, wherein said means for generating a reset pulse comprises: a two-input logic gate; means for providing the inverse of said master reset signal to one input terminal of said two-input logic gate; and means for providing a delayed version of said master reset signal to the other input terminal of said two-input logic gate.
Claim 10
Dependent Claim
119 words
A reset circuit for providing a global reset signal comprising: means for providing a VDD detect signal; means for generating a reset pulse in response to a master reset signal; means for shaping said reset pulse and outputting a modified reset pulse; and a logic device for receiving said VDD detect signal and said modified reset pulse, said logic device outputting said global reset signal, wherein said means for generating a reset pulse comprises: a two-input logic gate; means for providing the inverse of said master reset signal to one input terminal of said two-input logic gate; and means for providing a delayed version of said master reset signal to the other input terminal of said two-input logic gate.
Claim 11
Dependent Claim
31 words
A reset circuit as in claim 4 wherein said second path of said means for shaping further includes a Schmitt trigger connected between said plurality of inverters and said logic gate.
Claim 12
Dependent Claim
15 words
A reset circuit as in claim 4 wherein said logic gate is a NOR gate.
Claim 13
Dependent Claim
73 words
A reset circuit for providing a global reset signal comprising: means for providing a VDD detect signal; means for generating a reset pulse in response to a master reset signal; means for shaping said reset pulse and outputting a modified reset pulse; and a logic device for receiving said VDD detect signal and said modified reset pulse, said logic device outputting said global reset signal, wherein said logic device is an OR gate.
Claim 14
Dependent Claim
73 words
A reset circuit for providing a global reset signal comprising: means for providing a VDD detect signal; means for generating a reset pulse in response to a master reset signal; means for shaping said reset pulse and outputting a modified reset pulse; and a logic device for receiving said VDD detect signal and said modified reset pulse, said logic device outputting said global reset signal, wherein said logic device is an OR gate.
Claim 15
Dependent Claim
71 words
A reset circuit for providing a global reset signal comprising: a VDD detect circuit for providing a first signal; a set/reset latch for receiving an external reset signal and providing a reset pulse; a pulse shape circuit for receiving said reset pulse and providing a modified reset pulse; and a logic device for receiving said VDD detect signal and said modified reset pulse, said logic device providing said global reset signal.
Claim 16
Dependent Claim
71 words
A reset circuit for providing a global reset signal comprising: a VDD detect circuit for providing a first signal; a set/reset latch for receiving an external reset signal and providing a reset pulse; a pulse shape circuit for receiving said reset pulse and providing a modified reset pulse; and a logic device for receiving said VDD detect signal and said modified reset pulse, said logic device providing said global reset signal.
Claim 17
Dependent Claim
93 words
A reset circuit comprising: means for providing an OR function and generating a global reset signal; detect circuitry for detecting a predetermined voltage and providing a detect signal to said means for providing; means for receiving a user-generated reset signal; and means for delaying said user-generated reset signal and providing a delayed user-generated reset signal to said means for providing, wherein an edge of said user-generated reset signal triggers an edge of said global reset signal, and wherein the second edge of said global reset signal is determined by said means for delaying.
Claim 18
Dependent Claim
93 words
A reset circuit comprising: means for providing an OR function and generating a global reset signal; detect circuitry for detecting a predetermined voltage and providing a detect signal to said means for providing; means for receiving a user-generated reset signal; and means for delaying said user-generated reset signal and providing a delayed user-generated reset signal to said means for providing, wherein an edge of said user-generated reset signal triggers an edge of said global reset signal, and wherein the second edge of said global reset signal is determined by said means for delaying.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |