Remotely re-programmable program memory for a microcontroller

Claim 2

A re-programmable memory system with a microcontroller comprising, a remote host computer having a memory store with updated programs for execution by field microcontrollers, a single chip microcontroller having a single low voltage power supply, the microcontroller electrically communicating with said remote host computer and having electrically programmable and erasable read only memory cells and RAM memory cells, the electrically programmable and erasable read only memory cells connected as a main program store having power conversion means to generate voltage levels necessary for clearing the electrically programmable and erasable read only memory cells and writing therein using the low voltage power supply.

Claim 3

A re-programmable memory system with a microcontroller comprising, a remote host computer having a memory store with updated programs for execution by field microcontrollers, a single chip microcontroller having a single low voltage power supply, the microcontroller electrically communicating with said remote host computer and having PEROM and RAM memory cells, the PEROM memory cells connected as a main program store having power conversion means for clearing the PEROM cells and writing therein using the low voltage power supply, said power conversion means comprises a multi-stage charge pump having a low voltage input and a high voltage output and a clamp circuit means for holding the high voltage on command.

Claim 4

A re-programmable memory system with a microcontroller comprising, a remote host computer having a memory store with updated programs for execution by field microcontrollers, a single chip microcontroller having a single low voltage power supply, the microcontroller electrically communicating with said remote host computer and having PEROM and RAM memory cells, the PEROM memory cells connected as a main program store having power conversion means for clearing the PEROM cells and writing therein using the low voltage power supply, said power conversion means comprises a multi-stage charge pump having a low voltage input and a high voltage output and a clamp circuit means for holding the high voltage on command.

Claim 5

A re-programmable memory system with a microcontroller comprising, a remote host computer having a memory store with updated programs for execution by field microcontrollers, a single chip microcontroller having a single low voltage power supply, the microcontroller electrically communicating with said remote host computer and having PEROM and RAM memory cells, the PEROM memory cells connected as a main program store having power conversion means for clearing the PEROM cells and writing therein using the low voltage power supply, said power conversion means comprises a multi-stage charge pump having a low voltage input and a high voltage output and a discharge circuit means for discharging the high voltage on command.

Claim 6

A re-programmable memory system with a microcontroller comprising, a remote host computer having a memory store with updated programs for execution by field microcontrollers, a single chip microcontroller having a single low voltage power supply, the microcontroller electrically communicating with said remote host computer and having PEROM and RAM memory cells, the PEROM memory cells connected as a main program store having power conversion means for clearing the PEROM cells and writing therein using the low voltage power supply, said power conversion means comprises a multi-stage charge pump having a low voltage input and a high voltage output and a discharge circuit means for discharging the high voltage on command.

Claim 7

A program store circuit arrangement in an integrated circuit microcontroller of the type having an arithmetic logic unit, a plurality of registers associated with the arithmetic unit for executing program instructions and operating on data comprising, an array of electrically programmable and erasable read only memory transistors arranged in blocks whereby blocks of transistors may be simultaneously erased, an address bus connected to said array, said address bus in bidirectional communication with a port capable of receiving microinstructions from an external source, a data bus connected to said array as an output in a unidirectional manner and connected to microcontroller circuits on the data bus whereby said array is isolated from direct receipt of data from the data bus but communicates outwardly to the microcontroller circuits on the data bus, a random access memory array connected to the data bus, a bidirectional buffer separating the address bus from the data bus but permitting communication therebetween, a plurality of bidirectional I/O port means for bidirectional exchange of program address and data information, and a low voltage power supply having a connected charge pump means for converting the low voltage supply to a voltage level adequate for programming and erasing the electrically programmable and erasable read only memory transistors.

Claim 8

A program store circuit arrangement in an integrated circuit microcontroller of the type having an arithmetic logic unit, a plurality of registers associated with the arithmetic unit for executing program instructions and operating on data comprising, an array of electrically programmable and erasable read only memory transistors arranged in blocks whereby blocks of transistors may be simultaneously erased, an address bus connected to said array, said address bus in bidirectional communication with a port capable of receiving microinstructions from an external source, a data bus connected to said array as an output in a unidirectional manner and connected to microcontroller circuits on the data bus whereby said array is isolated from direct receipt of data from the data bus but communicates outwardly to the microcontroller circuits on the data bus, a random access memory array connected to the data bus, a bidirectional buffer separating the address bus from the data bus but permitting communication therebetween, a plurality of bidirectional I/O port means for bidirectional exchange of program address and data information, and a low voltage power supply having a connected charge pump means for converting the low voltage supply to a voltage level adequate for programming and erasing the electrically programmable and erasable read only memory transistors.

Claim 9

The circuit arrangement of claim 4 wherein the array of electrically programmable and erasable read only memory transistors comprise storage cells of two transistors including a select transistor and a bit storage transistor, both transistors operable from a single low voltage source.

Claim 10

The circuit arrangement of claim 5 wherein the bit storage transistor comprises a sense gate and a floating gate, the floating gate disposed over a region of thin tunnel oxide.

Claim 11

The circuit arrangement of claim 4 wherein said plurality of bidirectional I/O port means comprises, first and second bidirectional I/O port means connected to the address bus and the data bus for communication with an external program and data memory, and a third bidirectional I/O port means connected to the data bus for sharing tasks of the first and second port means.

Claim 12

In a microcontroller having an arithmetic logic unit, an accumulator and registers feeding the arithmetic logic unit, bidirectional I/O ports, an address bus and a data bus, the program store circuit improvement comprising, an array of electrically programmable and erasable read only memory transistors arranged in blocks whereby blocks of transistors may be simultaneously erased, the array connected to microcontroller circuits via the address and data buses, an array of random access memory transistors connected to the microcontroller circuits via the address and data buses, and a low voltage power supply having a connected charge pump means for converting the low voltage supply to a voltage level which programs and erases the electrically programmable and erasable read only memory transistors.

Claim 13

In a microcontroller having an arithmetic logic unit, an accumulator and registers feeding the arithmetic logic unit, bidirectional I/O ports, an address bus and a data bus, the program store circuit improvement comprising, an array of electrically programmable and erasable read only memory transistors arranged in blocks whereby blocks of transistors may be simultaneously erased, the array connected to microcontroller circuits via the address and data buses, an array of random access memory transistors connected to the microcontroller circuits via the address and data buses, and a low voltage power supply having a connected charge pump means for converting the low voltage supply to a voltage level which programs and erases the electrically programmable and erasable read only memory transistors.

Claim 14

The microcontroller of claim 8 wherein the array of electrically programmable and erasable memory transistors comprise a flash transistor array.

Claim 15

The microcontroller of claim 8 wherein the array of electrically programmable and erasable memory transistors comprise storage cells of two transistors including a select transistor and a bit storage transistor, both transistors operable from a single low voltage source.

Claim 16

The microcontroller of claim 8 wherein the bit storage transistor comprises a sense gate and a floating gate, the floating gate disposed over a region of thin tunnel oxide.

Claim 17

The microcontroller of claim 11 further comprising means for selectively discharging said sense gate.