Single transistor non-volatile electrically alterable semiconductor memory device

Claim 1

An improved programmable and erasable memory device in a semiconductor substrate, said device having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a common line, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of sites comprises a single transistor having a source region coupled to the common line, a drain region coupled to an associated one of the plurality of row address lines, the source and drain regions defining a channel region, a polycrystalline silicon floating gate having a top surface and edge surfaces located over a portion of the channel and a portion of the drain region, said control gate located over at least a portion of the floating gate, a portion of the channel not occupied by the floating gate, and over a portion of the source region, a thin insulating layer on the substrate surface over said source, drain and channel regions, and a thin tunneling insulator layer between said floating gate and said control gate, the improvement comprising an improved tunneling layer comprising: a dual insulator layer over said top surface and said edge surfaces of said floating gate, said dual layer comprised of an outer SiO 2 layer and an inner SiN x O y layer in direct contact with said floating gate where X is in the range of about one (1) to two (2) and y is in the range of about two (2) to three (3).