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US5492847A
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Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets
Assignee: National Semiconductor Corp
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Filing: 1994-08-01
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Granted: 1996-02-20
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Expires: 2014-08-01
Abstract
Abstract A method of processing a semiconductor device shapes a layer buried within a substrate of the semiconductor device. This layer has a conductivity the same as that of the substrate but has a higher doping level. In this process, a region of the layer is selected and ions of an opposite conductivity to the selected layer are counter-implanted in the region so that the doping level of the region is substantially canceled. A region of the layer adjacent to the counter-implanted region retains a higher doping level. Alternative techniques are employed to protect the doped region against the counter-implant. In a first approach, the layer is doped and subsequently a mask is formed on the surface of the substrate. The mask is furnished by a part of the semiconductor device, such as a spacer which is connected to the gate electrode after the dopant layer is formed in the substrate. After the mask is formed, ions are counter-implanted with the mask protecting the doped region. In a second approach, both the ion implant forming the doped layer and the counter-implant are performed after masking structures are formed, however the ion implant is a large-angle implant which implants ions beneath the masking structure while the counter-implant is a perpendicular implant so that regions beneath the masking structure are protected from cancellation.
Inventors
- 👤 Dah-Bin Kao
- 👤 Gregory S. Scott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:37
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/022; H10D30/0223; H10D30/0227; H10D30/0218; H10D30/60; H10D30/601; H10D30/605; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/919
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
97 words
A method of shaping a layer buried within a substrate of a semiconductor device, the layer having a conductivity the same as the substrate and having a higher doping level than the substrate, the method comprising the steps of: selecting a region of the layer; and counter-implanting ions of a conductivity opposite the conductivity of the layer into the selected region of the layer so that the layer doping level in the selected region is substantially canceled and a region of the layer outside the selected region having the higher doping level remains buried in the substrate.
Claim 2
Independent Claim
97 words
A method of shaping a layer buried within a substrate of a semiconductor device, the layer having a conductivity the same as the substrate and having a higher doping level than the substrate, the method comprising the steps of: selecting a region of the layer; and counter-implanting ions of a conductivity opposite the conductivity of the layer into the selected region of the layer so that the layer doping level in the selected region is substantially canceled and a region of the layer outside the selected region having the higher doping level remains buried in the substrate.
Claim 3
Dependent Claim
43 words
A method as in claim 1 wherein the counter-implanting step further comprises the step of: forming a mask structure on a surface of the substrate; wherein the region of the layer outside the selected region is protected from counter-implantation by the mask structure.
Claim 4
Dependent Claim
38 words
A method as in claim 2 wherein: a gate electrode is coupled to the surface of the substrate; a spacer is formed on a surface of the gate electrode; and the spacer and gate furnish the mask structure.
Claim 5
Dependent Claim
89 words
A method as in claim 1 wherein: a gate electrode is coupled to the surface of the substrate; the layer is formed by a large-angle implantation process inclining at an angle from a direction which is perpendicular to the substrate surface, the buried layer extending partially beneath the gate electrode; and the counter-implanting step implants ions from a direction substantially perpendicular to the substrate surface so that a portion of the layer region extending beneath the gate electrode substantially remains at the higher doping level region of the layer.
Claim 6
Dependent Claim
31 words
A method as in claim 1 wherein the semiconductor device is an n-channel device, the substrate and the layer have a p-type conductivity and the counter-implant is an n-type ion implant.
Claim 7
Dependent Claim
16 words
A method as in claim 5 wherein the n-type counter implant is a phosphorus ion implant.
Claim 8
Dependent Claim
31 words
A method as in claim 1 wherein the semiconductor device is a p-channel device, the substrate and the layer have an n-type conductivity and the counter-implant is a p-type ion implant.
Claim 9
Dependent Claim
16 words
A method as in claim 7 wherein the p-type counter implant is a boron ion implant.
Claim 10
Independent Claim
85 words
A method of forming an anti-punchthrough implant in a semiconductor device comprising the steps of: forming an anti-punchthrough implant region within a substrate, the anti-punchthrough implant having a conductivity the same as the substrate and having a higher doping level than the substrate; and counter-implanting ions of a conductivity opposite the conductivity of the anti-punchthrough implant into regions of the anti-punchthrough implant region so that the anti-punchthrough doping level in the regions is substantially canceled and an anti-punchthrough implant pocket remains buried in the substrate.
Claim 11
Independent Claim
85 words
A method of forming an anti-punchthrough implant in a semiconductor device comprising the steps of: forming an anti-punchthrough implant region within a substrate, the anti-punchthrough implant having a conductivity the same as the substrate and having a higher doping level than the substrate; and counter-implanting ions of a conductivity opposite the conductivity of the anti-punchthrough implant into regions of the anti-punchthrough implant region so that the anti-punchthrough doping level in the regions is substantially canceled and an anti-punchthrough implant pocket remains buried in the substrate.
Claim 12
Dependent Claim
37 words
A method as in claim 9 wherein the counter-implanting step further comprises the step of: forming a mask structure on a surface of the substrate; wherein the anti-punchthrough pocket is protected from counter-implantation by the mask structure.
Claim 13
Dependent Claim
57 words
A method as in claim 10 further comprising the steps of: coupling a gate electrode to the surface of the substrate; and forming a spacer on a lateral surface of the gate electrode subsequent to the anti-punchthrough implant step but preceding the counter-implanting step; wherein the spacer and gate furnish the mask structure for the anti-punchthrough pocket.
Claim 14
Dependent Claim
85 words
A method as in claim 9 further comprising the steps of: coupling a gate electrode to the surface of the substrate; and large-angle implanting the anti-punchthrough implant at an angle from a direction which is perpendicular to the substrate surface, the buried anti-punchthrough region extending partially beneath the gate electrode; wherein the counter implanting step implants ions from a direction substantially perpendicular to the substrate surface so that a portion of the anti-punchthrough region extending beneath the gate electrode substantially remains as the anti-punchthrough pocket.
Claim 15
Dependent Claim
36 words
A method as in claim 9 wherein the semiconductor device is an n-channel device, the substrate has a p-type conductivity, the anti-punchthrough implant is a p-type ion implant and the counter-implant is an n-type ion implant.
Claim 16
Dependent Claim
23 words
A method as in claim 13 wherein the anti-punchthrough implant is a boron ion implant and the counter-implant is a phosphorus ion implant.
Claim 17
Dependent Claim
36 words
A method as in claim 9 wherein the semiconductor device is a p-channel device, the substrate has an n-type conductivity, the anti-punchthrough implant is an n-type ion implant and the counter-implant is a p-type ion implant.
Claim 18
Dependent Claim
23 words
A method as in claim 15 wherein the anti-punchthrough implant is a phosphorus ion implant and the counter-implant is a boron ion implant.
Claim 19
Independent Claim
175 words
A method of fabricating a semiconductor device, comprising the steps of: forming two lightly doped implant regions of a first conductivity type each on a side of a gate electrode in a semiconductor substrate of a second conductivity type using the gate electrode as a mask structure, the gate electrode being coupled to the semiconductor substrate surface; forming two anti-punchthrough implant regions, having the second conductivity type and a higher doping level than the semiconductor substrate doping level, each buried in the semiconductor substrate under the lightly doped implant regions on a side of the gate electrode using the gate electrode as a mask structure; counter-implanting ions of the first conductivity type into regions of the two anti-punchthrough implant regions so that the anti-punchthrough doping level in the regions is substantially canceled and two anti-punchthrough implant pockets remain buried in the semiconductor substrate substantially beneath the edges of the gate electrode; and forming source and drain implant regions of the first conductivity type in the semiconductor substrate using the gate electrode as a mask structure.
Claim 20
Independent Claim
175 words
A method of fabricating a semiconductor device, comprising the steps of: forming two lightly doped implant regions of a first conductivity type each on a side of a gate electrode in a semiconductor substrate of a second conductivity type using the gate electrode as a mask structure, the gate electrode being coupled to the semiconductor substrate surface; forming two anti-punchthrough implant regions, having the second conductivity type and a higher doping level than the semiconductor substrate doping level, each buried in the semiconductor substrate under the lightly doped implant regions on a side of the gate electrode using the gate electrode as a mask structure; counter-implanting ions of the first conductivity type into regions of the two anti-punchthrough implant regions so that the anti-punchthrough doping level in the regions is substantially canceled and two anti-punchthrough implant pockets remain buried in the semiconductor substrate substantially beneath the edges of the gate electrode; and forming source and drain implant regions of the first conductivity type in the semiconductor substrate using the gate electrode as a mask structure.
Claim 21
Dependent Claim
37 words
A method as in claim 17 wherein the counter-implanting step further comprises the step of: forming spacers on lateral surfaces of the gate electrode; wherein the anti-punchthrough pockets are masked by the gate electrode and the spacers.
Claim 22
Dependent Claim
84 words
A method as in claim 17 wherein: the step of forming the anti-punchthrough implant region includes the step of large-angle implanting the anti-punchthrough implant at an angle from a direction which is perpendicular to the semiconductor substrate surface, each of the buried anti-punchthrough regions extending partially beneath the gate electrode; wherein the counter-implanting step implants ions from a direction substantially perpendicular to the semiconductor substrate surface so that portions of the anti-punchthrough regions extending beneath the gate electrode substantially remain as the anti-punchthrough pockets.
Claim 23
Dependent Claim
45 words
A method as in claim 17, wherein the lightly doped implant regions are implanted substantially in a region along the surface of the semiconductor substrate and the anti-punchthrough implant regions are implanted deeper in the semiconductor substrate, substantially adjacent to the lightly doped implant regions.
Claim 24
Dependent Claim
21 words
A method as in claim 17 wherein the gate electrode is coupled to the semiconductor substrate surface by an insulating layer.
Claim 25
Dependent Claim
54 words
A method as in claim 17 wherein the semiconductor device is an n-channel device, the semiconductor substrate has a p-type conductivity, the lightly doped implant is an n-type ion implant, the anti-punchthrough implant is a p-type ion implant, the counter-implant is an n-type ion implant and the source/drain implant is an n-type ion implant.
Claim 26
Dependent Claim
40 words
A method as in claim 22 wherein the lightly doped implant is a phosphorus ion implant, the anti-punchthrough implant is a boron ion implant, the counter-implant is a phosphorus ion implant and the source/drain implant is an arsenic ion implant.
Claim 27
Dependent Claim
54 words
A method as in claim 17 wherein the semiconductor device is a p-channel device, the semiconductor substrate has a n-type conductivity, the lightly doped implant is a p-type ion implant, the anti-punchthrough implant is an n-type ion implant, the counter-implant is a p-type ion implant and the source/drain implant is a p-type ion implant.
Claim 28
Dependent Claim
63 words
A method as in claim 24 wherein the lightly doped implant is a boron or BF 2 ion implant, the anti-punchthrough implant is a phosphorus ion implant, the counter-implant is a boron ion implant and the source/drain implant is a p-type ion implant selected from a boron ion implant, a BF 2 ion implant and a combination boron and BF 2 ion implant.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-02-19 | 1999-08-21 | 2000-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-19 | 2003-08-21 | 2004-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-19 | 2007-08-21 | 2008-02-20 | $7700.00 | Window Closed / Lapsed |