MIL-STD-1553 interface device having autonomous operation in all modes

Claim 2

An integrated circuit for interfacing a system with a MIL-STD-1553 data bus, the system having a host computer and volatile memory, wherein the integrated circuit is defined by a mode signal and a system reset signal and operates in one of several system selectable MIL-STD-1553 operating modes, said operating modes including 1) a bus controller mode, 2) a remote terminal mode, 3) a monitor mode and 4) concurrent monitor and remote terminal modes, said integrated circuit comprising: nonvolatile memory containing integrated circuit initialization data; means for receiving the mode signal indicative of the desired MIL-STD-1553 operating mode; means for selecting an operating mode from said several MIL-STD-1553 operating modes in response to the mode signal received by said means for receiving; means for detecting the system reset signal and for providing a reset signal which is active when the system reset signal is detected; and a microprocessor comprising; means for autonomously reading said initialization data when said reset signal is active; and means, responsive to the reset signal, for executing a predetermined sequence of signal processing operations indicative of the operating mode said integrated circuit is commanded to operate in as defined by said mode signal.

Claim 3

The integrated circuit of claim 1 wherein said microprocessor includes a plurality of registers which are loaded with said initialization data when said reset signal is active.

Claim 4

The integrated circuit of claim 2 wherein said plurality of registers includes a data register into which the starting address for a descriptor table of data, located in said volatile memory, is written to when said reset signal is active and said mode signal is indicative of the remote terminal mode of operation.

Claim 5

The integrated circuit of claim 2 wherein said plurality of registers includes a data register into which the starting address for a plurality of command blocks of data located in said volatile memory is written when said reset signal is active and said mode signal is indicative of the bus controller mode of operation.

Claim 6

The integrated circuit of claim 2 wherein said plurality of registers includes a data register into which the starting address for a descriptor table of data, located in said volatile memory, is written to when said reset signal is active and said mode signal is indicative of concurrent remote terminal and monitor mode of operation.

Claim 7

An integrated circuit for interfacing a system with a MIL-STD-1553 data bus, the system having a host computer and volatile memory, wherein the integrated circuit is defined by a mode signal and a system reset signal and operates in one of several system selectable MIL-STD-1553 operating modes, said operating modes including 1) a bus controller mode, 2) a remote terminal mode, 3) a monitor mode and 4) concurrent monitor and remote terminal modes, said integrated circuit comprising: nonvolatile memory containing integrated circuit initialization data; a plurality of registers; means for receiving the mode signal indicative of the desired MIL-STD-1553 operating mode; means for selecting an operating mode from said MIL-STD-1553 operating modes in response to the mode signal received by said means for receiving; means for detecting the system reset signal and for providing a reset signal which is active when the system reset signal is detected; and a microprocessor comprising: means for reading said initialization data when said reset signal is active without the intervention of the host computer and for loading said initialization data into said plurality of registers and said volatile memory in response to said system reset signal; and means, responsive to the reset signal, for executing a predetermined sequence of signal processing operations indicative of the operating mode said integrated circuit is commanded to operate in as defined by said mode signal.

Claim 8

An integrated circuit for interfacing a system with a MIL-STD-1553 data bus, the system having a host computer and volatile memory, wherein the integrated circuit is defined by a mode signal and a system reset signal and operates in one of several system selectable MIL-STD-1553 operating modes, said operating modes including 1) a bus controller mode, 2) a remote terminal mode, 3) a monitor mode and 4) concurrent monitor and remote terminal modes, said integrated circuit comprising: nonvolatile memory containing integrated circuit initialization data; a plurality of registers; means for receiving the mode signal indicative of the desired MIL-STD-1553 operating mode; means for selecting an operating mode from said MIL-STD-1553 operating modes in response to the mode signal received by said means for receiving; means for detecting the system reset signal and for providing a reset signal which is active when the system reset signal is detected; and a microprocessor comprising: means for reading said initialization data when said reset signal is active without the intervention of the host computer and for loading said initialization data into said plurality of registers and said volatile memory in response to said system reset signal; and means, responsive to the reset signal, for executing a predetermined sequence of signal processing operations indicative of the operating mode said integrated circuit is commanded to operate in as defined by said mode signal.

Claim 9

The integrated circuit of claim 6 wherein said plurality of registers includes a data register into which the starting address for a descriptor table of data located in said volatile memory is written to when said reset signal is active and said mode signal is indicative of the remote terminal mode of operation.

Claim 10

The integrated circuit of claim 6 wherein said plurality of registers includes a data register into which the starting address for a plurality of command blocks of data located in said volatile memory is written when said reset signal is active and said mode signal is indicative of the bus controller mode of operation.

Claim 11

The integrated circuit of claim 6 wherein said plurality of registers includes a data register into which the starting address for a descriptor table of data located in said volatile memory is written to when said reset signal is active and said mode signal is indicative of concurrent remote terminal and monitor mode of operation.

Claim 12

An integrated circuit for interfacing a system with a MIL-STD-1553 data bus, the system having a host computer and volatile memory, wherein the integrated circuit is defined by a mode signal and a system reset signal and autonomously operates in one of several system selectable MIL-STD-1553 operating modes, said several system selectable MIL-STD-1553 operating modes comprising: (1) a bus controller mode; (2) a remote terminal mode; (3) a monitor mode; and (4) concurrent monitor and remote terminal modes, said integrated circuit comprising: nonvolatile memory containing integrated circuit initialization data; a selector, responsive to the mode signal, for selecting an operating mode from said several MIL-STD-1553 operating modes, the mode signal indicative of the MIL-STD-1553 operating mode to be selected; a detector for detecting the system reset signal and for providing a reset signal in response to the system reset signal; and a microprocessor comprising: means for autonomously accessing said initialization data in response to said reset signal; and means, responsive to the reset signal, for executing a predetermined sequence of signal processing operations according to an operating mode selected from said several MIL-STD-1553 operating modes by said selector for selecting an operating mode in response to the mode signal.

Claim 13

An integrated circuit for interfacing a system with a MIL-STD-1553 data bus, the system having a host computer and volatile memory, wherein the integrated circuit is defined by a mode signal and a system reset signal and autonomously operates in one of several system selectable MIL-STD-1553 operating modes, said several system selectable MIL-STD-1553 operating modes comprising: (1) a bus controller mode; (2) a remote terminal mode; (3) a monitor mode; and (4) concurrent monitor and remote terminal modes, said integrated circuit comprising: nonvolatile memory containing integrated circuit initialization data; a selector, responsive to the mode signal, for selecting an operating mode from said several MIL-STD-1553 operating modes, the mode signal indicative of the MIL-STD-1553 operating mode to be selected; a detector for detecting the system reset signal and for providing a reset signal in response to the system reset signal; and a microprocessor comprising: means for autonomously accessing said initialization data in response to said reset signal; and means, responsive to the reset signal, for executing a predetermined sequence of signal processing operations according to an operating mode selected from said several MIL-STD-1553 operating modes by said selector for selecting an operating mode in response to the mode signal.

Claim 14

The integrated circuit of claim 10, wherein said microprocessor further comprises a plurality of registers which are loaded with said initialization data in response to said reset signal.

Claim 15

The integrated circuit of claim 11, wherein said plurality of registers comprises a data register into which a starting address for a descriptor table of data, located in said volatile memory, is written to in response to said reset signal when said mode signal is indicative of the terminal mode of operation.

Claim 16

The integrated circuit of claim 11, wherein said plurality of registers comprises a data register into which a starting address for a plurality of command blocks of data, located in said volatile memory, is written to in response to said reset signal when said mode signal is indicative of the bus controller mode of operation.

Claim 17

The integrated circuit of claim 11, wherein said plurality of registers comprises a data register into which a staffing address for a descriptor table of data, located in said volatile memory, is written to in response to said reset signal when said mode signal is indicative of the concurrent remote terminal and monitor mode of operation.