US5490147A
Expired / Lapsed
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Frame alignment circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1994-04-04
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Granted: 1996-02-06
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Expires: 2014-04-04
Abstract
Abstract A frame alignment circuit including at least a first series-to-parallel data converter having a shift register for accumulating series data, a latch circuit for converting the accumulated data into parallel data and a variable counter for dividing a clock signal into a divided clock signal. The frame alignment circuit further includes a pattern detector which detects a frame alignment pattern of the parallel data, a determining circuit which determines a deviation of alignment based on a reference frame alignment signal and the detected frame alignment pattern and a shift controlling circuit for controlling at least a dividing ratio of the variable counter based on a deviation of alignment signal output by the frame alignment circuit.
Inventors
- 👤 Kazuo Kubo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:34
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0608
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
290 words
A frame alignment circuit comprising: at least one series-to-parallel data converting means including: a shift register for receiving a clock signal and a first parallel data signal, accumulating the first parallel data signal and outputting an accumulated data signal; a latch circuit for receiving the accumulated data signal and a divided clock signal, for latching the accumulated data signal, and for outputting a second parallel data signal; and a variable counter for receiving the clock signal and a shifting signal, for dividing the clock signal, and outputting the divided clock signal; a pattern detecting means for receiving the second parallel data signal, for detecting a frame alignment pattern of the second parallel data signal, and for outputting a frame alignment pattern detection result signal; a frame alignment determining means for receiving the frame alignment pattern detection result signal, for detecting a deviation of alignment of the frame alignment pattern detection result signal, and for outputting a deviation of alignment signal; a shift controlling means for receiving the deviation of alignment signal and the frame alignment pattern detection result signal, for expanding the deviation of alignment signal, and for outputting the shifting signal and a selecting signal; and wherein the shift controlling means includes: an encoder circuit which receives the frame alignment pattern detection result signal, encodes the frame alignment pattern detection result signal into a plurality of binary bits and outputs an encoded signal; at least one counter which receives the encoder signal, forms the shifting signal, and outputs the shifting signal to the at least one series-to-parallel converter; and a latch circuit which receives the encoded signal, retains a residual bit of the plurality of bits of the encoded signal, and outputs the residual bit as the selecting signal.
Claim 2
Dependent Claim
290 words
A frame alignment circuit comprising: at least one series-to-parallel data converting means including: a shift register for receiving a clock signal and a first parallel data signal, accumulating the first parallel data signal and outputting an accumulated data signal; a latch circuit for receiving the accumulated data signal and a divided clock signal, for latching the accumulated data signal, and for outputting a second parallel data signal; and a variable counter for receiving the clock signal and a shifting signal, for dividing the clock signal, and outputting the divided clock signal; a pattern detecting means for receiving the second parallel data signal, for detecting a frame alignment pattern of the second parallel data signal, and for outputting a frame alignment pattern detection result signal; a frame alignment determining means for receiving the frame alignment pattern detection result signal, for detecting a deviation of alignment of the frame alignment pattern detection result signal, and for outputting a deviation of alignment signal; a shift controlling means for receiving the deviation of alignment signal and the frame alignment pattern detection result signal, for expanding the deviation of alignment signal, and for outputting the shifting signal and a selecting signal; and wherein the shift controlling means includes: an encoder circuit which receives the frame alignment pattern detection result signal, encodes the frame alignment pattern detection result signal into a plurality of binary bits and outputs an encoded signal; at least one counter which receives the encoder signal, forms the shifting signal, and outputs the shifting signal to the at least one series-to-parallel converter; and a latch circuit which receives the encoded signal, retains a residual bit of the plurality of bits of the encoded signal, and outputs the residual bit as the selecting signal.
Claim 3
Dependent Claim
302 words
A frame alignment circuit comprising: at least one series-to-parallel data converting means including: a shift register for receiving a clock signal and a first parallel data signal, accumulating the first parallel data signal and outputting an accumulated data signal; a latch circuit for receiving the accumulated data signal and a divided clock signal, for latching the accumulated data signal and outputting a second parallel data signal; and a variable counter for receiving the clock signal and a shifting signal, for dividing the clock signal and for outputting the divided clock signal; a pattern detecting means for receiving the second parallel data signal, for detecting a frame alignment pattern of the second parallel data signal, and for outputting a frame alignment pattern detection result signal; a frame alignment determining means for receiving the frame alignment pattern detection result signal, for detecting a deviation of alignment of the frame alignment pattern detection result signal, and for outputting a deviation of alignment signal; a shift controlling means for receiving the deviation of alignment signal and the frame alignment pattern detection result signal, for expanding the deviation of alignment signal, and for outputting the shifting signal and a selecting signal; and wherein the shift controlling means includes: an encoder circuit which receives the frame alignment pattern detection result signal, encodes the frame alignment pattern detection result signal into a plurality of binary bits and outputs an encoded signal; at least one counter which receives the encoded signal, forms the shifting signal, and outputs the shifting signal to the at least one series-to-parallel converter; and a calculating circuit which receives the encoded signal and the selecting signal, adds the encoded signal to the selecting signal, and outputs a calculation signal and wherein the at least one counter circuit receives the calculation signal and forms the shifting signal.
Claim 4
Dependent Claim
302 words
A frame alignment circuit comprising: at least one series-to-parallel data converting means including: a shift register for receiving a clock signal and a first parallel data signal, accumulating the first parallel data signal and outputting an accumulated data signal; a latch circuit for receiving the accumulated data signal and a divided clock signal, for latching the accumulated data signal and outputting a second parallel data signal; and a variable counter for receiving the clock signal and a shifting signal, for dividing the clock signal and for outputting the divided clock signal; a pattern detecting means for receiving the second parallel data signal, for detecting a frame alignment pattern of the second parallel data signal, and for outputting a frame alignment pattern detection result signal; a frame alignment determining means for receiving the frame alignment pattern detection result signal, for detecting a deviation of alignment of the frame alignment pattern detection result signal, and for outputting a deviation of alignment signal; a shift controlling means for receiving the deviation of alignment signal and the frame alignment pattern detection result signal, for expanding the deviation of alignment signal, and for outputting the shifting signal and a selecting signal; and wherein the shift controlling means includes: an encoder circuit which receives the frame alignment pattern detection result signal, encodes the frame alignment pattern detection result signal into a plurality of binary bits and outputs an encoded signal; at least one counter which receives the encoded signal, forms the shifting signal, and outputs the shifting signal to the at least one series-to-parallel converter; and a calculating circuit which receives the encoded signal and the selecting signal, adds the encoded signal to the selecting signal, and outputs a calculation signal and wherein the at least one counter circuit receives the calculation signal and forms the shifting signal.
Claim 5
Dependent Claim
29 words
The frame alignment circuit as claimed in claim 2, wherein the shift controlling means further comprises a latch circuit which receives the calculation signal and forms the selecting signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-05 | 1999-08-07 | 2000-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-05 | 2003-08-07 | 2004-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-05 | 2007-08-07 | 2008-02-06 | $7700.00 | Window Closed / Lapsed |