US5327434A
Expired / Lapsed
US
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Frame alignment circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1992-10-06
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Granted: 1994-07-05
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Expires: 2012-10-06
Abstract
Abstract A frame alignment circuit comprises a first series-to-parallel data converting means comprising a first shift register for accumulating a series data, a first latch circuit for converting the series data into a first parallel data and a first counter for dividing a clock signal into a divided clock signal; a second series-to-parallel data converting means comprising a second shift register for accumulating the first parallel data outputted from the first series-to-parallel data converting means, a second latch circuit for latching the first parallel data and outputting the first parallel data which is converted into a second parallel data and a second counter for further dividing the divided clock signal of the first counter; a frame alignment determining means for detecting a deviation of alignment based on a frame alignment pattern; and a shift controlling means for controlling at least a divided ratio of the second counter based on the deviation of alignment outputted by the frame alignment determining means.
Inventors
- 👤 Kazuo Kubo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:51
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0608
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
301 words
A frame alignment circuit comprising: a first series-to-parallel data converting means including: a first shift register for receiving a clock signal and a series data signal, accumulating the series data signal and outputting an accumulated series data signal; a first latch circuit for receiving the accumulated series data signal and a divided clock signal, converting the accumulated series data signal into a first parallel data signal and outputting the parallel data signal; and a first counter for receiving the clock signal, dividing the clock signal into the divided clock signal and outputting the divided clock signal; a second series-to-parallel data converting means including: a second shift register for receiving the parallel data signal and the divided clock signal, accumulating the parallel data signal and outputting an accumulated parallel data signal; a second latch circuit for receiving the accumulated parallel data signal and a second divided clock signal, further converting the accumulated parallel data signal into a second parallel data signal and outputting an accumulated second parallel data signal; and a second counter for receiving the divided clock signal and a shifting signal, further dividing the divided clock signal and outputting the second divided clock signal; pattern detecting means for receiving said accumulated second parallel data signal, detecting frame alignment pattern and outputting a frame alignment pattern detection result signal; a frame alignment determining means for receiving said frame alignment pattern detection result signal, detecting a deviation of alignment of the frame alignment pattern and outputting a deviation of alignment signal; a shift controlling means for receiving the deviation of alignment signal and the frame alignment pattern detection result signal, for expanding the deviation of alignment signal and outputting the shifting signal; and wherein the second counter, in response to the shifting signal, shifts an order of the second parallel data signal.
Claim 2
Dependent Claim
301 words
A frame alignment circuit comprising: a first series-to-parallel data converting means including: a first shift register for receiving a clock signal and a series data signal, accumulating the series data signal and outputting an accumulated series data signal; a first latch circuit for receiving the accumulated series data signal and a divided clock signal, converting the accumulated series data signal into a first parallel data signal and outputting the parallel data signal; and a first counter for receiving the clock signal, dividing the clock signal into the divided clock signal and outputting the divided clock signal; a second series-to-parallel data converting means including: a second shift register for receiving the parallel data signal and the divided clock signal, accumulating the parallel data signal and outputting an accumulated parallel data signal; a second latch circuit for receiving the accumulated parallel data signal and a second divided clock signal, further converting the accumulated parallel data signal into a second parallel data signal and outputting an accumulated second parallel data signal; and a second counter for receiving the divided clock signal and a shifting signal, further dividing the divided clock signal and outputting the second divided clock signal; pattern detecting means for receiving said accumulated second parallel data signal, detecting frame alignment pattern and outputting a frame alignment pattern detection result signal; a frame alignment determining means for receiving said frame alignment pattern detection result signal, detecting a deviation of alignment of the frame alignment pattern and outputting a deviation of alignment signal; a shift controlling means for receiving the deviation of alignment signal and the frame alignment pattern detection result signal, for expanding the deviation of alignment signal and outputting the shifting signal; and wherein the second counter, in response to the shifting signal, shifts an order of the second parallel data signal.
Claim 3
Dependent Claim
18 words
A frame alignment circuit as claimed in claim 1, wherein the first counter is a fixed dividing counter.
Claim 4
Dependent Claim
18 words
A frame alignment circuit as claimed in claim 1, wherein the second counter is a variable dividing counter.
Claim 5
Dependent Claim
58 words
A frame alignment circuit as claimed in claim 1, wherein the shift controlling means comprises: an encoder circuit which receives the frame alignment pattern detection result signal, encodes the frame alignment pattern detection result signal and outputs an encoded signal; and a counter circuit which receives the encoded signal, forms the shifting signal and outputs the shifting signal.
Claim 6
Dependent Claim
33 words
A frame alignment circuit as claimed in claim 4, wherein the shift controlling means further comprises: a latch circuit which receives the encoded signal, forms a selecting signal and outputs a selecting signal.
Claim 7
Dependent Claim
41 words
A frame alignment circuit as claimed in claim 5, further comprising signal rearranging means for receiving the second parallel data signal and the selecting signal, for rearranging an order of the parallel data signal and outputting a rearranged parallel data signal.
Claim 8
Dependent Claim
83 words
A frame alignment circuit as claimed in claim 1, wherein the shift controlling means comprises: an encoder circuit which receives the frame alignment pattern detection result signal, encodes the frame alignment pattern detection result signal and outputs an encoded signal; a calculating circuit which receives the encoded signal and a selecting signal, adds the encoded signal to the selecting signal and outputs a calculation signal; and a counter circuit which receives the calculation signal, forms the shifting signal and outputs the shifting signal.
Claim 9
Dependent Claim
33 words
A frame alignment circuit as claimed in claim 7, wherein the shift controlling means further comprising: a latch circuit which receives the calculation signal, forms the selecting signal and outputs the selecting signal.
Claim 10
Dependent Claim
40 words
The frame alignment circuit as claimed in claim 8, further comprising: signal rearranging means for receiving the parallel data signal and the shifting signal, for rearranging an order of the parallel data signal and outputting a rearranged parallel data signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-04 | 2002-01-03 | 2002-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-04 | 2006-01-03 | 2006-07-05 | $7700.00 | Window Closed / Lapsed |