Patent US5490113A successfully refreshed from Google Patents.
US5490113A
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US
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Memory stream buffer
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-06-15
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Granted: 1996-02-06
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Expires: 2014-06-15
Abstract
Abstract A memory system has a stream buffer with several performance-enhancing features. Two distinct sets of latches receive data from the memory array. One set feeds the stream buffer, while the other holds memory data that is destined for a system bus. The dual-latch configuration allows stream buffer fills to proceed even if system bus stalls prevent the memory data latch from being timely emptied. The memory controller prefetches a number of data blocks depending on the interleave factor of the memory system, as well as in response to control information from the CPU that can override the interleave-based number in some system configurations. The stream buffer employs a history buffer containing the addresses of recently-read memory locations in order to declare a new stream. The addresses of memory reads are normally entered into the history buffer on a round-robin basis. However, the addresses of those reads that hit in the stream buffer are not entered, thus improving the overall efficiency of the stream buffer. Also, the memory refresh controller treats stream buffer hits as memory refresh opportunities. Finally, a block of control/status registers within the memory controller is accessible in two distinct address ranges, so that the memory controller may easily be used in different hardware configurations.
Inventors
- 👤 David A. Tatosian
- 👤 Paul M. Goodwin
- 👤 Kurt M. Thaller
- 👤 Donald W. Smelser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:32
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1075; G11C7/1051
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
212 words
Apparatus, comprising: a memory array having an output port coupled to a memory array bus; a first latch whose data input is coupled to said memory array bus; a second latch whose data input is coupled to said memory array bus; a data storage buffer having an input port and an output port, the input port being coupled to the data output of said second latch; means for selectively coupling the data output of said first latch and the output port of said data storage buffer to a system bus over which data from said first latch and said data storage buffer is to be transferred; means for enabling said first latch to be loaded from said memory array with data to be subsequently transferred over said system bus; means for disabling said first latch from being loaded from said memory array when said first latch contains data to be transferred over said system bus and said system bus is unavailable for the transfer of the data contained in said first latch; and means for enabling said second latch to be loaded from said memory array with data to be subsequently stored in said data storage buffer while said first latch is disabled from being loaded from said memory array is disabled.
Claim 2
Dependent Claim
212 words
Apparatus, comprising: a memory array having an output port coupled to a memory array bus; a first latch whose data input is coupled to said memory array bus; a second latch whose data input is coupled to said memory array bus; a data storage buffer having an input port and an output port, the input port being coupled to the data output of said second latch; means for selectively coupling the data output of said first latch and the output port of said data storage buffer to a system bus over which data from said first latch and said data storage buffer is to be transferred; means for enabling said first latch to be loaded from said memory array with data to be subsequently transferred over said system bus; means for disabling said first latch from being loaded from said memory array when said first latch contains data to be transferred over said system bus and said system bus is unavailable for the transfer of the data contained in said first latch; and means for enabling said second latch to be loaded from said memory array with data to be subsequently stored in said data storage buffer while said first latch is disabled from being loaded from said memory array is disabled.
Claim 3
Dependent Claim
92 words
Apparatus according to claim 1, wherein said coupling means comprises: a multiplexer having a select input upon which a select signal is to be received, a first data input coupled to the data output of said first latch, a second data input coupled to the output port of said data storage buffer, and a data output coupled to said system bus; and means for generating said select signal in a manner effective to enable the transfer of data from said first data latch and said data storage buffer over said system bus.
Claim 4
Dependent Claim
157 words
Apparatus for use in conjunction with a memory module in a memory system, comprising: means for storing a control bit denoted a fill limit indicator; and means for prefetching blocks of data in a manner dependent upon the state of said fill limit indicator, the number of blocks of data that are prefetched while said fill limit indicator is not set being one less than I max /I actual , where I max is a maximum degree to which said memory module can be interleaved with other memory modules in said memory system, and I actual is an actual degree of such interleaving, and the number of blocks of data that are prefetched while said fill limit indicator is set being the lesser of (a) the number of data blocks that would be prefetched if said fill limit indicator were not set, and (b) a predetermined number that is substantially less than said maximum degree of interleaving.
Claim 5
Dependent Claim
157 words
Apparatus for use in conjunction with a memory module in a memory system, comprising: means for storing a control bit denoted a fill limit indicator; and means for prefetching blocks of data in a manner dependent upon the state of said fill limit indicator, the number of blocks of data that are prefetched while said fill limit indicator is not set being one less than I max /I actual , where I max is a maximum degree to which said memory module can be interleaved with other memory modules in said memory system, and I actual is an actual degree of such interleaving, and the number of blocks of data that are prefetched while said fill limit indicator is set being the lesser of (a) the number of data blocks that would be prefetched if said fill limit indicator were not set, and (b) a predetermined number that is substantially less than said maximum degree of interleaving.
Claim 6
Dependent Claim
20 words
Apparatus according to claim 3, wherein said maximum degree of interleaving is four, and wherein said predetermined number is 1.
Claim 7
Dependent Claim
16 words
Apparatus according to claim 4, wherein the size of each fetched data block is 32 bytes.
Claim 8
Dependent Claim
224 words
Apparatus, comprising: means for receiving read commands from a processor, each read command specifying a corresponding memory location to be read; a history buffer for storing address values each corresponding to the address of the memory location specified by a corresponding one of said read commands; means for determining for each of said read commands whether a predetermined relationship exists between the address of the memory location specified thereby and any of the address values stored in said history buffer; means for prefetching data from a memory at memory locations each sequentially following the memory location specified by a corresponding read command for which said predetermined relationship is determined to exist; means for storing the prefetched data into a stream buffer; means for determining for each of said read commands whether the data from the memory location specified thereby is stored in said stream buffer; means for fetching from said stream buffer the data that is determined to be stored in said stream buffer; means for returning the data fetched from said stream buffer to said processor; and means for refraining from storing into said history buffer an address value corresponding to the address of the memory location specified by each of said read commands for which the data from the memory location specified thereby is determined to be stored in said stream buffer.
Claim 9
Dependent Claim
224 words
Apparatus, comprising: means for receiving read commands from a processor, each read command specifying a corresponding memory location to be read; a history buffer for storing address values each corresponding to the address of the memory location specified by a corresponding one of said read commands; means for determining for each of said read commands whether a predetermined relationship exists between the address of the memory location specified thereby and any of the address values stored in said history buffer; means for prefetching data from a memory at memory locations each sequentially following the memory location specified by a corresponding read command for which said predetermined relationship is determined to exist; means for storing the prefetched data into a stream buffer; means for determining for each of said read commands whether the data from the memory location specified thereby is stored in said stream buffer; means for fetching from said stream buffer the data that is determined to be stored in said stream buffer; means for returning the data fetched from said stream buffer to said processor; and means for refraining from storing into said history buffer an address value corresponding to the address of the memory location specified by each of said read commands for which the data from the memory location specified thereby is determined to be stored in said stream buffer.
Claim 10
Dependent Claim
117 words
Apparatus, comprising: 1) means for monitoring operation of a memory system to determine whether the following conditions exist: a) a pending memory read transaction that would otherwise require access to a memory array in said memory system has hit in a stream buffer in said memory system so that data requested thereby can be obtained from said stream buffer rather than said memory array; b) refresh of said memory array has not yet been performed during a refresh window interval; and c) there are no additional pending memory transactions either using or requiring the use of said memory array; and 2) means for refreshing said memory array upon the simultaneous existence of all of the foregoing conditions.
Claim 11
Dependent Claim
117 words
Apparatus, comprising: 1) means for monitoring operation of a memory system to determine whether the following conditions exist: a) a pending memory read transaction that would otherwise require access to a memory array in said memory system has hit in a stream buffer in said memory system so that data requested thereby can be obtained from said stream buffer rather than said memory array; b) refresh of said memory array has not yet been performed during a refresh window interval; and c) there are no additional pending memory transactions either using or requiring the use of said memory array; and 2) means for refreshing said memory array upon the simultaneous existence of all of the foregoing conditions.
Claim 12
Dependent Claim
124 words
Apparatus, comprising: a latch coupled to a bus to receive an address therefrom; a first decoder coupled to said latch and configured to assert a first select signal on an output thereof when said latch contains a first predetermined address value; a second decoder coupled to said latch and configured to assert a second select signal on an output thereof when said second decoder is enabled and said latch contains a second predetermined address value different from said first predetermined address value; means for indicating whether either of said first and second select signals is asserted; and means coupled to said bus and to said second decoder for enabling and disabling said second decoder in response to a corresponding command received from said bus.
Claim 13
Dependent Claim
124 words
Apparatus, comprising: a latch coupled to a bus to receive an address therefrom; a first decoder coupled to said latch and configured to assert a first select signal on an output thereof when said latch contains a first predetermined address value; a second decoder coupled to said latch and configured to assert a second select signal on an output thereof when said second decoder is enabled and said latch contains a second predetermined address value different from said first predetermined address value; means for indicating whether either of said first and second select signals is asserted; and means coupled to said bus and to said second decoder for enabling and disabling said second decoder in response to a corresponding command received from said bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-05 | 1999-08-07 | 2000-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-05 | 2003-08-07 | 2004-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-05 | 2007-08-07 | 2008-02-06 | $7700.00 | Window Closed / Lapsed |