Patent US5489796A successfully refreshed from Google Patents.
US5489796A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit resistor comprising amorphous silicon
Assignee: Texas Instruments Inc
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Filing: 1995-01-06
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Granted: 1996-02-06
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Expires: 2015-01-06
Abstract
Abstract The device hereof provides an integrated circuit resistor (34) comprising amorphous or noncrystalline semiconducting material. Further advantages can be gained in area by forming the noncrystalline semiconductor resistor in a non-planar fashion (i. e. with a vertical construction) wherein a first electrical contact is made to the resistor on its bottom surface and a second electrical contact is made to the resistor on its top surface. Other devices, systems and methods are also disclosed.
Inventors
- 👤 Mark G. Harward
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:38
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615; H10B; H10B10/00; H10B10/15; H10D84/40; H10D84/401; H10D84/403; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
100 words
A circuit comprising: a) an input; b) an output; c) a transistor having a first, a second, and a third terminal, said first terminal being coupled to said output, said second terminal being coupled to said input, and said third terminal being coupled to a first bias voltage; and d) a doped, vertical noncrystalline silicon resistor having a first and a second terminal, said first terminal being connected to said first terminal of said transistor with a first metal alloy interposed therebetween, and said second terminal being connected to a second bias voltage connection with another metal alloy interposed therebetween.
Claim 2
Dependent Claim
100 words
A circuit comprising: a) an input; b) an output; c) a transistor having a first, a second, and a third terminal, said first terminal being coupled to said output, said second terminal being coupled to said input, and said third terminal being coupled to a first bias voltage; and d) a doped, vertical noncrystalline silicon resistor having a first and a second terminal, said first terminal being connected to said first terminal of said transistor with a first metal alloy interposed therebetween, and said second terminal being connected to a second bias voltage connection with another metal alloy interposed therebetween.
Claim 3
Dependent Claim
12 words
The circuit of claim 1, wherein said transistor is an NMOS transistor.
Claim 4
Dependent Claim
12 words
The circuit of claim 1, wherein said transistor is an NPN transistor.
Claim 5
Dependent Claim
168 words
A semiconductor memory cell comprising: a) a first transistor having a first, a second, and a third terminal; b) a second transistor having a first, a second, and a third terminal, said first terminal of said second transistor being coupled to said second terminal of said first transistor, said second terminal of said second transistor being coupled to said first terminal of said first transistor, and said third terminal of said second transistor being coupled to said third terminal of said first transistor; c) a first doped, vertical noncrystalline semiconductor resistor having a first and a second terminal, said first terminal being coupled to said first terminal of said first transistor with a first metal alloy interposed therebetween; and d) a second vertical noncrystalline semiconductor resistor having a first and a second terminal, said first terminal being coupled to said first terminal of said second transistor with another metal alloy interposed therebetween, and said second terminal being coupled to said second terminal of said first noncrystalline semiconductor resistor.
Claim 6
Dependent Claim
168 words
A semiconductor memory cell comprising: a) a first transistor having a first, a second, and a third terminal; b) a second transistor having a first, a second, and a third terminal, said first terminal of said second transistor being coupled to said second terminal of said first transistor, said second terminal of said second transistor being coupled to said first terminal of said first transistor, and said third terminal of said second transistor being coupled to said third terminal of said first transistor; c) a first doped, vertical noncrystalline semiconductor resistor having a first and a second terminal, said first terminal being coupled to said first terminal of said first transistor with a first metal alloy interposed therebetween; and d) a second vertical noncrystalline semiconductor resistor having a first and a second terminal, said first terminal being coupled to said first terminal of said second transistor with another metal alloy interposed therebetween, and said second terminal being coupled to said second terminal of said first noncrystalline semiconductor resistor.
Claim 7
Dependent Claim
15 words
The memory cell of claim 4, wherein said first and second transistors are PMOS transistors.
Claim 8
Dependent Claim
15 words
The memory cell of claim 4, wherein said first and second transistors are PNP transistors.
Claim 9
Dependent Claim
21 words
The memory cell of claim 4, wherein said first and second vertical noncrystalline silicon resistors are doped vertical noncrystalline silicon resistors.
Claim 10
Dependent Claim
165 words
A semiconductor memory cell comprising: a first transistor having a first, a second, and a third terminal; a second transistor having a first, a second, and a third terminal, said first terminal of said second transistor being coupled to said second terminal of said first transistor, said second terminal of said second transistor being coupled to said first terminal of said first transistor, and said third terminal of said second transistor being coupled to said third terminal of said first transistor; a first doped, vertical noncrystalline silicon resistor having a first and a second terminal, said first terminal being coupled to said first terminal of said first transistor with a first metal alloy interposed therebetween; and a second doped vertical noncrystalline silicon resistor having a first and a second terminal, said first terminal being coupled to said first terminal of said second transistor with another metal alloy interposed therebetween, and said second terminal being coupled to said second terminal of said first noncrystalline semiconductor resistor.
Claim 11
Dependent Claim
165 words
A semiconductor memory cell comprising: a first transistor having a first, a second, and a third terminal; a second transistor having a first, a second, and a third terminal, said first terminal of said second transistor being coupled to said second terminal of said first transistor, said second terminal of said second transistor being coupled to said first terminal of said first transistor, and said third terminal of said second transistor being coupled to said third terminal of said first transistor; a first doped, vertical noncrystalline silicon resistor having a first and a second terminal, said first terminal being coupled to said first terminal of said first transistor with a first metal alloy interposed therebetween; and a second doped vertical noncrystalline silicon resistor having a first and a second terminal, said first terminal being coupled to said first terminal of said second transistor with another metal alloy interposed therebetween, and said second terminal being coupled to said second terminal of said first noncrystalline semiconductor resistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-05 | 1999-08-07 | 2000-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-05 | 2003-08-07 | 2004-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-05 | 2007-08-07 | 2008-02-06 | $7700.00 | Window Closed / Lapsed |