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Patent US5489541A successfully refreshed from Google Patents.
US5489541A
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Process of fabricating a bipolar junction transistor
Assignee: United Microelectronics Corp
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Filing: 1995-04-14
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Granted: 1996-02-06
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Expires: 2015-04-14
Abstract
Abstract A process of fabricating a bipolar junction transistor forms, on the substrate, a masking layer including an opening, an intermediate masking portion surrounded by the opening and an outer masking portion. The masking layer consists of a pad oxide and a silicon nitride. A photoresist is then formed on the outer masking portion. A first ion implantation process at a relatively low dose and a relatively high energy is performed to form a base region underlying the intermediate masking portion, and a second ion implantation process at a relatively high dose and a relatively low energy is performed to form a base contact region underlying the opening. Then, the photoresist is removed. A field oxide is grown in the opening of the masking layer, followed by removing the masking layer. A highly-doped polysilicon layer is deposited over the structure, and a rapid thermal annealing process is performed to diffuse the impurities within the polysilicon layer into the substrate to form an emitter region in the base region and to form a collector contact region, by using the field oxide as a mask.
Inventors
- 👤 Sheng-Hsing Yang
- 👤 Ying-Tzung Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:57
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; Y; Y10; Y10S; Y10S148/00; Y10S148/01
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
145 words
A method for fabricating a bipolar junction transistor, comprising the following steps of: (a) forming a first masking layer with an opening on a face of a substrate, said first masking layer including an intermediate masking portion surrounded by said opening and an outer masking portion; (b) forming a second masking layer on said outer masking portion; (c) ion implanting in said substrate a base region underlying said intermediate masking portion, and a base contact region underlying said opening; (d) removing said second masking layer; (e) forming an insulating region overlying said base contact region; (f) removing said first masking layer; (g) forming a doped conductive layer over the substrate; and (h) diffusing impurities within said conductive layer into said substrate to form an emitter region in said base region and to form a collector contact region, by using said insulating region as a mask.
Claim 2
Independent Claim
145 words
A method for fabricating a bipolar junction transistor, comprising the following steps of: (a) forming a first masking layer with an opening on a face of a substrate, said first masking layer including an intermediate masking portion surrounded by said opening and an outer masking portion; (b) forming a second masking layer on said outer masking portion; (c) ion implanting in said substrate a base region underlying said intermediate masking portion, and a base contact region underlying said opening; (d) removing said second masking layer; (e) forming an insulating region overlying said base contact region; (f) removing said first masking layer; (g) forming a doped conductive layer over the substrate; and (h) diffusing impurities within said conductive layer into said substrate to form an emitter region in said base region and to form a collector contact region, by using said insulating region as a mask.
Claim 3
Dependent Claim
61 words
A method as claimed in claim 1, wherein said step (c) comprises the steps of ion implantation with a first dose and a first energy to form said base region, and ion implantation with a second dose which is higher than said first dose and a second energy which is lower than said first energy to form said base contact region.
Claim 4
Dependent Claim
76 words
A method as claimed in claim 2, wherein the ion implantation for forming said base region uses boron ions with a dose of between about 2×10 12 to 2×10 14 atoms/cm 2 and an energy of between about 50 to 100 KeV; and wherein the ion implantation for forming said base contact region uses BF 2 ions with a dose greater than 1×10 15 atoms/cm 2 and an energy of between approximately 20 and 30 KeV.
Claim 5
Dependent Claim
75 words
A method as claimed in claim 2, wherein the ion implantation for said base region uses BF 2 ions with a dose of between approximately 2×10 12 and 2×10 14 atoms/cm 2 and an energy of between approximately 50 and 100 KeV; and wherein the ion implantation for said base contact region uses BF 2 ions with a dose greater than 1×10 15 atoms/cm 2 and an energy of between approximately 20 and 30 KeV.
Claim 6
Dependent Claim
21 words
A method as claimed in claim 2, wherein said base region has a junction depth shallower than said base contact region.
Claim 7
Dependent Claim
46 words
A method as claimed in claim 2, wherein said step (a) comprises the steps of forming by oxidation a pad oxide over said substrate; forming a silicon nitride over said pad oxide; and patterning said silicon nitride and pad oxide to complete said first masking layer.
Claim 8
Dependent Claim
30 words
A method as claimed in claim 6, wherein said pad oxide has a thickness of about 200-500 angstroms, and wherein said silicon nitride has a thickness of about 1000-2000 angstroms.
Claim 9
Dependent Claim
16 words
A method as claimed in claim 7, wherein said second masking layer is made from photoresist.
Claim 10
Dependent Claim
27 words
A method as claimed in claim 6, wherein said step (e) comprises the step of growing a field oxide in said opening of said first masking layer.
Claim 11
Dependent Claim
21 words
A method as claimed in claim 9, wherein said field oxide has a thickness of between about 5000 to 20000 angstroms.
Claim 12
Dependent Claim
16 words
A method as claimed in claim 2, wherein said doped conductive layer is made from polysilicon.
Claim 13
Dependent Claim
40 words
A method as claimed in claim 11, wherein said step (h) comprises the step of performing a rapid thermal annealing process to diffuse impurities from said polysilicon layer into the substrate regions which are not covered by said insulating region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-05 | 1999-08-07 | 2000-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-05 | 2003-08-07 | 2004-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-05 | 2007-08-07 | 2008-02-06 | $7700.00 | Window Closed / Lapsed |