US5488695A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video peripheral board in expansion slot independently exercising as bus master control over system bus in order to relief control of host computer
Assignee: Acoustic Technology LLC
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Filing: 1995-03-16
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Granted: 1996-01-30
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Expires: 2015-03-16
Abstract
Abstract A video peripheral board for providing video I/O capabilities to a general purpose host computer. The video peripheral board comprises a video I/O port configured to connect a video device, a bus interface circuit, and a processor. The bus interface circuit is configured to connect the video peripheral board into a system bus of the host computer, and is capable of becoming bus master of the system bus. The bus interface circuit includes a bus master address generator, a data buffer and bus control logic that provides and receives bus control signals to and from the system bus to effect read and write operations over the system bus independent of the central processing unit of the host computer. The processor controls the bus interface circuit and the video I/O port to effect transfer of video data between the video I/O port and storage of the host computer, the video data passing through the video I/O port in real time.
Inventors
- 👤 Daniel F. Cutter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:49
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/40; H04N21/41; H04N21/414; H04N21/4143; G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; H04N5/00; H04N5/76; H04N5/765
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
367 words
A video peripheral board having connections for an expansion slot of a general purpose computer for providing video I/O capabilities to said general purpose host computer, said general purpose computer having a system bus, data storage accessed by read and write operations over said system bus, and a central processing unit, said system bus being controllable by said central processing unit (CPU) or by an external device connected to said system bus, the video peripheral board comprising: a video I/O port connected to a video device; a bus interface circuit connected to said system bus of the host computer and to said video I/O port, said bus interface circuit including a bus master address generator that generates addresses of said storage for read and write operations over said system bus, a data buffer storing video data for transfer to or from said system bus, and bus control logic that provides and receives bus control signals to and from said system bus to effect read and write operations over said system bus independent of said central processing unit of said general purpose host computer, said bus interface circuit thereby being bus master of said system bus; and a processor connected to control said video I/O port and said bus control logic of said bus interface circuit to effect transfer of video data between said video I/O port and said data buffer land transfer between said data buffer and said storage of the host computer at addresses generated by said bus master address generator, said video data passing through said video I/O port in real time wherein: the video peripheral board has two or more data paths through the video peripheral board to said bus interface circuit, each said data path having two ends and a priority, at least one said data path being connected between said bus interface circuit and said video I/O port; and said processor is configured to control said bus interface circuit and said data paths to effect real time transfers of data over said data paths, and to schedule completion of a transfer over a higher-priority one of said data paths in preference to a transfer over a lower-priority one of said data paths.
Claim 2
Dependent Claim
367 words
A video peripheral board having connections for an expansion slot of a general purpose computer for providing video I/O capabilities to said general purpose host computer, said general purpose computer having a system bus, data storage accessed by read and write operations over said system bus, and a central processing unit, said system bus being controllable by said central processing unit (CPU) or by an external device connected to said system bus, the video peripheral board comprising: a video I/O port connected to a video device; a bus interface circuit connected to said system bus of the host computer and to said video I/O port, said bus interface circuit including a bus master address generator that generates addresses of said storage for read and write operations over said system bus, a data buffer storing video data for transfer to or from said system bus, and bus control logic that provides and receives bus control signals to and from said system bus to effect read and write operations over said system bus independent of said central processing unit of said general purpose host computer, said bus interface circuit thereby being bus master of said system bus; and a processor connected to control said video I/O port and said bus control logic of said bus interface circuit to effect transfer of video data between said video I/O port and said data buffer land transfer between said data buffer and said storage of the host computer at addresses generated by said bus master address generator, said video data passing through said video I/O port in real time wherein: the video peripheral board has two or more data paths through the video peripheral board to said bus interface circuit, each said data path having two ends and a priority, at least one said data path being connected between said bus interface circuit and said video I/O port; and said processor is configured to control said bus interface circuit and said data paths to effect real time transfers of data over said data paths, and to schedule completion of a transfer over a higher-priority one of said data paths in preference to a transfer over a lower-priority one of said data paths.
Claim 3
Dependent Claim
28 words
The video peripheral board of claim 1 wherein said at least one said data path comprises a compression/decompression coder, and another said data path is a subsample path.
Claim 4
Dependent Claim
16 words
The video peripheral board of claim 1 wherein one said data path is an audio path.
Claim 5
Dependent Claim
18 words
The peripheral board of claim 1 wherein said scheduling is priority based to maintain integrity of high-priority paths.
Claim 6
Dependent Claim
65 words
The peripheral board of claim 4 wherein: said lower-priority path comprises a subsampler for subsampling video data into the display memory of the host computer; said higher-priority path connects the host computer to a video device at said video I/O port; and said processor halts said subsample path in order to maintain the integrity of the real time transfer of data on said higher-priority path.
Claim 7
Dependent Claim
14 words
The peripheral board of claim 5 wherein said higher-priority path comprises a compression/decompression coder.
Claim 8
Dependent Claim
46 words
The peripheral board of claim 1 wherein the video device presents or consumes data at said video I/O port in real time, the peripheral board further comprising a first-in-first-out queuing store (FIFO) to store said data between said bus interface circuit and said video I/O port.
Claim 9
Dependent Claim
22 words
The peripheral board of claim 1 wherein said bus control logic blocks the data into blocks for transfer over said system bus.
Claim 10
Dependent Claim
12 words
The peripheral board of claim 1 wherein said processor comprises a microprocessor.
Claim 11
Dependent Claim
48 words
The peripheral board of claim 1 wherein said processor controls said bus master address generator to specify particular addresses in said storage so as to store said data that had been input into said video I/O port in a sequential organization into said storage in a non-sequential organization.
Claim 12
Dependent Claim
48 words
The peripheral board of claim 1 wherein: said peripheral board includes a demultiplexer connected to said bus interface circuit to demultiplex data transferred to said peripheral board from said storage into a portion to control said peripheral board and a portion to output on said video I/O port.
Claim 13
Dependent Claim
306 words
A video peripheral board having connections for an expansion slot of a general purpose computer for providing video I/O capabilities to said general purpose host computer, said general purpose computer having a system bus, data storage accessed by read and write operations over said system bus, and a central processing unit, said system bus being controllable by said central processing unit (CPU) or by an external device connected to said system bus, the video peripheral board comprising: a video I/O port connected to a video device; a bus interface circuit connected to said system bus of the host computer and to said video I/O port, said bus interface circuit including a bus master address generator that generates addresses of said storage for read and write operations over said system bus, a data buffer storing video data for transfer to or from said system bus, and bus control logic that provides and receives bus control signals to and from said system bus to effect read and write operations over said system bus independent of said central processing unit of said general purpose host computer, said bus interface circuit thereby being bus master of said system bus; and a processor connected to control said video I/O port and said bus control logic of said bus interface circuit to effect transfer of video data between said video I/O port and said data buffer and transfer between said data buffer and said storage of the host computer at addresses generated by said bus master address generator, said video data passing through said video I/O port in real time, wherein said processor controls said bus master address generator to specify particular addresses in said storage so as to store said data that had been input into said video I/O port in a sequential organization into said storage in a non-sequential organization.
Claim 14
Dependent Claim
306 words
A video peripheral board having connections for an expansion slot of a general purpose computer for providing video I/O capabilities to said general purpose host computer, said general purpose computer having a system bus, data storage accessed by read and write operations over said system bus, and a central processing unit, said system bus being controllable by said central processing unit (CPU) or by an external device connected to said system bus, the video peripheral board comprising: a video I/O port connected to a video device; a bus interface circuit connected to said system bus of the host computer and to said video I/O port, said bus interface circuit including a bus master address generator that generates addresses of said storage for read and write operations over said system bus, a data buffer storing video data for transfer to or from said system bus, and bus control logic that provides and receives bus control signals to and from said system bus to effect read and write operations over said system bus independent of said central processing unit of said general purpose host computer, said bus interface circuit thereby being bus master of said system bus; and a processor connected to control said video I/O port and said bus control logic of said bus interface circuit to effect transfer of video data between said video I/O port and said data buffer and transfer between said data buffer and said storage of the host computer at addresses generated by said bus master address generator, said video data passing through said video I/O port in real time, wherein said processor controls said bus master address generator to specify particular addresses in said storage so as to store said data that had been input into said video I/O port in a sequential organization into said storage in a non-sequential organization.
Claim 15
Dependent Claim
25 words
The peripheral board of claim 12 wherein said data stored in said storage in non-sequential organization are interspersed with control information related to said data.
Claim 16
Dependent Claim
57 words
The peripheral board of claim 12 wherein said data transferred from said data buffer to said storage are divided into portions, successive portions being of generally different lengths, and said generated addresses are generated in sequentially increasing order for storing data within each of said portions, said addresses being generated to leave a gap between said portions.
Claim 17
Dependent Claim
50 words
The peripheral board of claim 12 wherein said data storage is the RAM of the host computer, and said host computer manages the transfer of said data between said RAM and a mass storage device of said host computer, said processor being connected to communicate with said host's transfer management.
Claim 18
Dependent Claim
264 words
A video peripheral board having connections for an expansion slot of a general purpose computer for providing video I/O capabilities to said general purpose host computer, said general purpose computer having a system bus, data storage accessed by read and write operations over said system bus, and a central processing unit, said system bus being controllable by said central processing unit (CPU) or by an external device connected to said system bus, the video peripheral board comprising: a video I/O port connected to a video device; a bus interface circuit connected to said system bus of the host computer and to said video I/O port, said bus interface circuit including a bus master address generator that generates addresses of said storage for read and write operations over said system bus, a data buffer storing video data for transfer to or from said system bus, and bus control logic that provides and receives bus control signals to and from said system bus to effect read and write operations over said system bus independent of said central processing unit of said general purpose host computer, said bus interface circuit thereby being bus master of said system bus; and a processor connected to control said video I/O port and said bus control logic of said bus interface circuit to effect transfer of video data between said video I/O port and said data buffer and transfer between said data buffer and said storage of the host computer at addresses generated by said bus master address generator, said video data passing through said video I/O port in real time.
Claim 19
Dependent Claim
264 words
A video peripheral board having connections for an expansion slot of a general purpose computer for providing video I/O capabilities to said general purpose host computer, said general purpose computer having a system bus, data storage accessed by read and write operations over said system bus, and a central processing unit, said system bus being controllable by said central processing unit (CPU) or by an external device connected to said system bus, the video peripheral board comprising: a video I/O port connected to a video device; a bus interface circuit connected to said system bus of the host computer and to said video I/O port, said bus interface circuit including a bus master address generator that generates addresses of said storage for read and write operations over said system bus, a data buffer storing video data for transfer to or from said system bus, and bus control logic that provides and receives bus control signals to and from said system bus to effect read and write operations over said system bus independent of said central processing unit of said general purpose host computer, said bus interface circuit thereby being bus master of said system bus; and a processor connected to control said video I/O port and said bus control logic of said bus interface circuit to effect transfer of video data between said video I/O port and said data buffer and transfer between said data buffer and said storage of the host computer at addresses generated by said bus master address generator, said video data passing through said video I/O port in real time.
Claim 20
Dependent Claim
96 words
The video peripheral board of claim 16 wherein said processor is responsive to control commands from said CPU of the general purpose host computer to begin transfer of video data, control commands from the CPU of the general purpose host computer to stop transfer of video data, and directives from the CPU of the general purpose host computer describing addresses in said storage for transfers of data to control said bus interface circuit to transfer data between said data buffer and said storage as bus master of said system bus between said start and stop commands.
Claim 21
Dependent Claim
14 words
The video peripheral board of claim 17 wherein said storage is random access memory.
Claim 22
Dependent Claim
88 words
The video peripheral board of claim 16 further comprising an audio I/O port configured to connect a source/destination device for audio; and wherein said processor is connected to control said audio I/O port and said bus control logic to also effect transfer of audio data between said audio I/O port and said data buffer and transfer between said data buffer and said storage of the host computer at addresses generated by said bus master address generator, said audio data passing through said audio I/O port in real time.
Claim 23
Dependent Claim
13 words
The video peripheral board of claim 16 wherein said processor comprises a microprocessor.
Claim 24
Dependent Claim
57 words
The peripheral board of claim 16 wherein said storage is the RAM of the host computer, and said host computer also has a mass storage device controllable by said central processing unit of said host computer, said processor exchanging control messages with said central processing unit relating to transfers between said RAM and said mass storage device.
Claim 25
Dependent Claim
24 words
The video peripheral board of claim 16 wherein said bus control logic blocks the video data into blocks for transfer over said system bus.
Claim 26
Dependent Claim
66 words
The video peripheral board of claim 16 wherein said processor controls said bus interface circuit to effect real time transfer of data from said data storage to the video peripheral board through said bus interface circuit; and to demultiplex said data transferred to said video peripheral board into a portion to control said video peripheral board and a portion to output on said video I/O port.
Claim 27
Dependent Claim
29 words
The video peripheral board of claim 16 further comprising: a compression/decompression coder between said video I/O port and said bus interface circuit for compressing or decompressing said video data.
Claim 28
Dependent Claim
276 words
A peripheral board having connections for an expansion slot of a general purpose computer for providing video I/O capabilities to said general purpose host computer, said general purpose computer having a system bus, data storage accessed by read and write operations over said system bus, and a central processing unit, said system bus being controllable by said central processing unit (CPU) or by an external device connected to said system bus, the video peripheral board comprising: a video I/O port connected to a video device; a bus interface circuit connected to said system bus of the host computer and to said video I/O port, said bus interface circuit including a bus master address generator that generates addresses of said storage for read and write operations over said system bus, a data buffer storing video data for transfer to or from said system bus, and bus control logic that provides and receives bus control signals to and from said system bus to effect read and write operations over said system bus independent of said central processing unit of said general purpose host computer, said bus interface circuit thereby being bus master of said system bus; and a processor connected to control said video I/O port and said bus control logic of said bus interface circuit to effect transfer of video data between said video I/O port and said data buffer and transfer between said data buffer and said storage of the host computer at addresses generated by said bus master address generator, said video data passing through said video I/O port in real time, further comprising a FIFO between said input port and said bus control circuit.
Claim 29
Dependent Claim
276 words
A peripheral board having connections for an expansion slot of a general purpose computer for providing video I/O capabilities to said general purpose host computer, said general purpose computer having a system bus, data storage accessed by read and write operations over said system bus, and a central processing unit, said system bus being controllable by said central processing unit (CPU) or by an external device connected to said system bus, the video peripheral board comprising: a video I/O port connected to a video device; a bus interface circuit connected to said system bus of the host computer and to said video I/O port, said bus interface circuit including a bus master address generator that generates addresses of said storage for read and write operations over said system bus, a data buffer storing video data for transfer to or from said system bus, and bus control logic that provides and receives bus control signals to and from said system bus to effect read and write operations over said system bus independent of said central processing unit of said general purpose host computer, said bus interface circuit thereby being bus master of said system bus; and a processor connected to control said video I/O port and said bus control logic of said bus interface circuit to effect transfer of video data between said video I/O port and said data buffer and transfer between said data buffer and said storage of the host computer at addresses generated by said bus master address generator, said video data passing through said video I/O port in real time, further comprising a FIFO between said input port and said bus control circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-29 | 1999-07-31 | 2000-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-29 | 2003-07-31 | 2004-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-29 | 2007-07-31 | 2008-01-30 | $7700.00 | Window Closed / Lapsed |