Multiple concurrent display system

Claim 2

A display system providing for the simultaneous accelerated generation of independent video information for presentation on multiple independent displays, said display system comprising: a) a video memory having a plurality of addressable storage locations, each storage location providing for the storage of data representing a component of an independent displayable image, said video memory providing for accelerated accessing of said addressable storage locations within pages of said addressable storage locations; b) a data buffer having a first data interface coupled to said video memory and a second interface data interface coupleable to an external host computer system to provide a direct data transfer path to said video memory; and c) a video controller, coupled to said video memory, to provide a plurality of sets of output display control and data signals coupleable to a respective plurality of video displays, said video controller including means for accessing said video memory in a predetermined addressing pattern to access a sequence of said components corresponding to a plurality of said independent displayable images where said components of a first independent displayable image are interleaved with said components of a second independent displayable image in predetermined ones of said pages of said addressable storage locations, said video controller further including control means, responsive to said accessed sequence of said components, for generating said plurality of sets of output display control and data signals where each said set of said plurality of said output display control and data signals corresponds to a respective one of said independent displayable images.

Claim 3

The display system of claim 1 wherein said predetermined addressing pattern includes a repeating pattern of sequentially accessing consecutive successive series of respective components of each said independent displayable image.

Claim 4

The display system of claim 2 wherein said video controller provides first output display control and data signals to a first video display and second output display control and data signals to a second video display and wherein said predetermined addressing pattern includes alternatingly accessing components to be provided to said first and second displays.

Claim 5

The display system of claim 1 wherein said accessing means provides for the interleaved storage of said components of said first and second independent displayable images in proportion to the respective display resolutions and color depth of said first and second independent displayable images.

Claim 6

The display system of claim 1, 3 or 4 wherein said video memory includes a first portion for storing control data and a second portion for storing said components of said first and second independent displayable images, said first portion being further subdivided to provide respective control data storage areas for said first and second independent displayable images, said video controller being coupled to said video memory to permit the reading and writing of control data to said first portion.

Claim 7

A display subsystem providing for the simultaneous redisplay of independent images to multiple independent display devices, said display subsystem comprising: a) a video memory storage unit providing for the storage and retrieval of pixel data in response to address control signals, said pixel data including a first display image and a second display image, said pixel data corresponding to said first display image being interleaved with said pixel data corresponding to said second display image; b) a first display interface providing for the transfer of first display control and data signals; c) a second display interface providing for the transfer of second display control and data signals; d) a data buffer coupled to said video memory storage unit and coupleable to an external data bus to permit the direct transfer of data between said external data bus and said video memory storage unit; and e) a video controller coupled to said video memory storage unit, said data buffer, and to said first and second display interfaces, said video controller generating said addressing signals to retrieve said pixel data in a sequential address sequence, said video controller further generating said first and second display and control signals from respective subsets of said pixel data corresponding to said first and second display images.

Claim 8

A display subsystem providing for the simultaneous redisplay of independent images to multiple independent display devices, said display subsystem comprising: a) a video memory storage unit providing for the storage and retrieval of pixel data in response to address control signals, said pixel data including a first display image and a second display image, said pixel data corresponding to said first display image being interleaved with said pixel data corresponding to said second display image; b) a first display interface providing for the transfer of first display control and data signals; c) a second display interface providing for the transfer of second display control and data signals; d) a data buffer coupled to said video memory storage unit and coupleable to an external data bus to permit the direct transfer of data between said external data bus and said video memory storage unit; and e) a video controller coupled to said video memory storage unit, said data buffer, and to said first and second display interfaces, said video controller generating said addressing signals to retrieve said pixel data in a sequential address sequence, said video controller further generating said first and second display and control signals from respective subsets of said pixel data corresponding to said first and second display images.

Claim 9

The display subsystem of claim 6 wherein said video memory storage unit includes a control register store that provides for the storage of first and second sets of control data defining the operation of said video controller relative to the generation of said addressing signals and said first and second display and control signals.

Claim 10

The display subsystem of claim 7 wherein said pixel data corresponding to said first and second display images is interleaved in relation to the respective display resolution and color depths of said first and second display images.

Claim 11

A computer system providing for the simultaneous independent display of computer images on a plurality of independent video output devices, said computer system comprising: a) an addressable video data memory providing for the storage of register control data in a first memory area and image data in a second memory area; b) a first interface coupleable to a first video output device; c) a second interface coupleable to a second video output device; and d) an integrated circuit coupled to said video data memory, said integrated circuit including: i) control means for addressing said video data memory to transfer said register control data and said image data between said video data memory and said control means, said control means providing for the logical establishment of first and second sets of said register control data in said first memory area, said control means providing for the mutually interleaved storage of predetermined sub-portions of first and second image data sets in said second memory area, said control means further providing for the sequential addressing of said second memory area to store and retrieve respective interleaved sub-portions of said first and second image data sets; ii) sequencer means, responsive to the interleave of said sub-portions as provided said control means, for sequentially providing said respective sub-portions of said first and second image data sets separately to said first and second interfaces; and iii) buffer means for providing a first data path between said video data memory and said control means, a second data path between said video data memory and said sequencer means, and a third data path between said video data memory and an external data interface.

Claim 12

A computer system providing for the simultaneous independent display of computer images on a plurality of independent video output devices, said computer system comprising: a) an addressable video data memory providing for the storage of register control data in a first memory area and image data in a second memory area; b) a first interface coupleable to a first video output device; c) a second interface coupleable to a second video output device; and d) an integrated circuit coupled to said video data memory, said integrated circuit including: i) control means for addressing said video data memory to transfer said register control data and said image data between said video data memory and said control means, said control means providing for the logical establishment of first and second sets of said register control data in said first memory area, said control means providing for the mutually interleaved storage of predetermined sub-portions of first and second image data sets in said second memory area, said control means further providing for the sequential addressing of said second memory area to store and retrieve respective interleaved sub-portions of said first and second image data sets; ii) sequencer means, responsive to the interleave of said sub-portions as provided said control means, for sequentially providing said respective sub-portions of said first and second image data sets separately to said first and second interfaces; and iii) buffer means for providing a first data path between said video data memory and said control means, a second data path between said video data memory and said sequencer means, and a third data path between said video data memory and an external data interface.

Claim 13

The computer system of claim 7 wherein said addressable video data memory includes a burst mode accessible random access memory for storing said image data.